The ground rules:
- in every DQS group, the DQS, DQ and DM signals need to be matched.
- DQS groups are independent from each other.
- CA signals need to be matched.
- DQS must be shorter than CA for any chip.
You can route CA either as a tree, or as a bus, the typical pinout on DDR3 ICs makes the bus routing a bit easier.
The DDR3 controller will pretty much always support read leveling, i.e. it will delay the sampling point for the signals in each DQ group to match the length of the CA signals for that IC.
If the controller does not also support write leveling (i.e. delaying the outgoing data transfer in each group to match the CA timing), then you should also length-match the DQS groups to be a tiny bit shorter than CA for each IC, so the distance between the command and the data is the same for all ICs.
If the controller does support write leveling, these delays are added inside the controller and don't need to be implemented as traces.
If you have multiple ranks, I'd route ODT along with CA.
The controller will nonetheless run a calibration sequence to determine actual timings and where the optimal sampling points are.