I am designing a pcb using LDDR3 for the first time. There are some questions that confuse me.

  1. Should I match all DQ,DQS,DM signals with equal length?
  2. Should I match the common address CA signals with each other and with other DQ, DQS, DM signals at the same length? Is there a document you can recommend me about DDR3 pcb design?

Thank you very much.


1 Answer 1


The ground rules:

  • in every DQS group, the DQS, DQ and DM signals need to be matched.
  • DQS groups are independent from each other.
  • CA signals need to be matched.
  • DQS must be shorter than CA for any chip.

You can route CA either as a tree, or as a bus, the typical pinout on DDR3 ICs makes the bus routing a bit easier.

The DDR3 controller will pretty much always support read leveling, i.e. it will delay the sampling point for the signals in each DQ group to match the length of the CA signals for that IC.

If the controller does not also support write leveling (i.e. delaying the outgoing data transfer in each group to match the CA timing), then you should also length-match the DQS groups to be a tiny bit shorter than CA for each IC, so the distance between the command and the data is the same for all ICs.

If the controller does support write leveling, these delays are added inside the controller and don't need to be implemented as traces.

If you have multiple ranks, I'd route ODT along with CA.

The controller will nonetheless run a calibration sequence to determine actual timings and where the optimal sampling points are.

  • \$\begingroup\$ Thank you for reply. How should the CK (clk differential) signal relate to other signals? \$\endgroup\$
    – user295040
    Dec 9, 2021 at 8:10
  • \$\begingroup\$ CK is the clock for the CA group, so it needs to be routed alongside and matched with the CA group. CA and the DQS groups each form an independent clocked parallel bus, and the only constraint between groups is that the data transfer for a command must be within a specific cycle. The delay elements in the DQS groups can only extend, but not shorten runtime, so that's why DQS must be shorter than CK for each IC. \$\endgroup\$ Dec 9, 2021 at 10:04
  • \$\begingroup\$ "DQS may not be shorter than CA for any chip." That is wrong. It is the other way around. \$\endgroup\$ Jan 10, 2022 at 19:49
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    \$\begingroup\$ @TimmyBrolin, oops, thanks! DQS must be shorter than CA -- that's why DIMMs route CA in a loop through the middle before going to the first chip. \$\endgroup\$ Jan 11, 2022 at 5:25
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    \$\begingroup\$ I would include the RESET line in the CA group as well. The standard is a bit unclear if this is required or not, but it does not hurt. \$\endgroup\$ Jan 11, 2022 at 17:51

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