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I am trying to create a simulation of an IEPE sensor circuit and get it to match measured behavior of something like a PCB 378B02 microphone connected to such a supply.

IEPE sensor-side amplifier implementations appear to be a trade secret however I'm hoping there's a general model I can use to evaluate my supply circuit performance over different cable lengths/types.

I found this:

enter image description here

which was taken from here.

I've attempted to implement it below, guessing at the piezo R and C values (not sure their values are highly critical) and using an ideal cable for now:

enter image description here

I also added a resistor to the drain of the MOSFET as it seemed to help. The simulation is here.

In the lab with a 2mA constant current, I've found the sensor input conductor on the power supply typically ends up biased to around 10-12V but with this simulation it is at 23V and the current is not held steady. The MOSFET is only in saturation for half of the input sine wave cycle whereas I understand for a Source Follower arrangement it's normally always kept in saturation.

How can I modify this to better represent typical IEPE sensor/supply behavior?

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There's no way your sim will work: the n-FET body diode will kill it (no cheating: you can't disable it in the sim and call it good.)

A p-FET in that spot actually works as a follower. Since their diagram didn't specify, but you're calling it a 'follower' and source is tied to a positive voltage, that'd be reasonable. Once the circuit stabilizes around the threshold point (it takes a while - let the sim run) then you get the voltage swing on the cable. Try it here

One note: the output coupling has a tiny voltage as it is working as a high-pass filter with a relatively low frequency (250 Hz). The output swing would be much larger with a faster dV/dt impulse, larger cap or larger load resistor.

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  • \$\begingroup\$ This does work much better, thank you. The DC bias on the cable is only +2V instead of 10-12V I see in practice, any idea how this is achieved? \$\endgroup\$
    – davegravy
    Dec 9, 2021 at 22:09
  • \$\begingroup\$ The bias you see on the cable varies with the Vgs threshold of the FET. In the simulation it's set to -1.5V; if it is set higher (more negative) the bias increases. So the signal will swing +/- the Vgs threshold, what you would expect for a follower. \$\endgroup\$ Dec 9, 2021 at 22:51
  • \$\begingroup\$ Right. Practically speaking MOSFET Vgs thresholds look like they max out around 5V, so is it safe to say there's usually additional gain stages that contribute to this bias? \$\endgroup\$
    – davegravy
    Dec 9, 2021 at 23:51
  • \$\begingroup\$ Try adding a resistor between source and gate - 100k or so. This shifts up the operating point. \$\endgroup\$ Dec 10, 2021 at 2:50
  • \$\begingroup\$ You can also lift the signal up using additional p-FETs in series, with gate connected to drain. Diodes in series would work too. \$\endgroup\$ Dec 11, 2021 at 21:03

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