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I know what the difference between interlaced and progressive scan is: in progressive video modes, the monitor displays all the lines of a video field sequentially. In interlaced, it displays them on alternate lines, then displays a second video field offset downwards slightly on the other alternate lines.

The question is, how does the display circuitry know which approach to use? What characteristic of the signal says "interlaced"? Is this carried on the sync pulses somehow?

The context may be VGA display modes, or computer video output using composite or RGB signals to a CRT monitor.

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  • \$\begingroup\$ "the context may be": hmm, I think pinpointing a context here is key. What video signal standards do you refer to that have both interleaved and non-interleaved modes? \$\endgroup\$ Dec 10, 2021 at 11:58
  • \$\begingroup\$ Context is sending these from a computer which has arbitrarily configurable video output, e.g. X11 Modelines or Raspi hdmi_timings, both of which have "interlaced on/off" as an option. \$\endgroup\$
    – pjc50
    Dec 10, 2021 at 12:26

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This comes up with digital working - flat panels, frame grabbers and the like. These systems that deal with interlace have to do the right thing with the scan line data to reconstruct full frames. On the other hand, analog CRTs just 'figure it out' (by design actually) and make the correct raster for interlace.

How?

Say you're tasked with capturing video and so have to worry about this. The vertical sync vs. horizontal sync timing gives a clue to the capture system how to deal with the input.

Succinctly,

  • interlace: the 'second' field vsync starts in the middle of a line
  • progressive: vsync always aligns with or near h-sync

1080i50 example:

enter image description here

From here: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/430417/dm8148-1080i-interlace-video-capture-with-vps_vip_fid_detect_mode_vsync-mode

Analog video with embedded sync (composite, component or sync-on-green RGB) requires a sync separator block that teases out H / V sync and blanking give you digital H and V signals as well as blank. V sync specifically is detected by looking at the composite sync equalization / serration pulses.

VGA with TTL sync already sends H and V separately, but nonetheless can also support interlace or progressive in the same way as embedded sync, by modifying V sync timing on the second field.

Either way, once you have the digital H, V and H blank signals, you test for V sync changing state during the active (non-blank) interval. A very simple way to do this is to clock the H blank signal period with the leading edge of V sync. If interlace is in use, first field will clock low, second field will clock high. If the field flip-flop never toggles (that is, V sync always falls during blank), congratulations, you have progressive.

A now-obsolete chip, the LM1881, did this for you. Link: https://www.ti.com/lit/ds/symlink/lm1881.pdf In addition to H and V sync, it outputs a toggling field signal, that won't toggle if progressive is in use. The circuit diagram shows the basic clocked-flop principle for field detect.

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  • \$\begingroup\$ The diagram/picture says it describes how NTSC sync signals work, but either that is just plain wrong or just a gross oversimplification to convey the idea of interlaced signaling but just FYI that is not how NTSC signals look like in real life. The HSYNC serration pulses are missing and VSYNC pulse is three lines long. \$\endgroup\$
    – Justme
    Dec 11, 2021 at 13:37
  • \$\begingroup\$ Oddly enough, I wasn’t able to find a good diagram for NTSC or PAL out in the wild showing separate signals. Maybe you could find one. I swapped the diagram for one that shows 1080i50, illustrating the principle of VSYNC half-line offset for field 2. \$\endgroup\$ Dec 11, 2021 at 19:04
  • \$\begingroup\$ That 1080i picture is good for showing separate sync signals. NTSC and PAL are technically just color encoding methods for composite signals so that might explain why under those names no separate sync diagrams are found. The underlying scanning formats are called 525i and 625i which can exist using separate sync signals and the diagram of 1080i works fine (just the numbers are different). \$\endgroup\$
    – Justme
    Dec 11, 2021 at 19:39
  • \$\begingroup\$ I’m well aware of this. I’m saying that, oddly enough, I just couldn’t find a handy diagram for NTSC / PAL with the separate syncs alongside composite, showing the sync and field sequence. Surprising, given that such a diagram would be in any DMSD or DENC datasheet. Then again, legacy TV (though it seems to live on in low-end backup cameras.) \$\endgroup\$ Dec 11, 2021 at 19:52
  • \$\begingroup\$ I think I'm going to award this the tick for including a diagram, but I've upvoted all helpful answers. \$\endgroup\$
    – pjc50
    Dec 11, 2021 at 22:03
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The “magic” about interlacing is that it doesn't need any additional circuit.

In a CRT, the horizontal lines aren't really displayed horizontally. They are slanted so that the right end of a scanline is at the same vertical position as the left end of the next scanline. During the horizontal backporch, only the horizontal position is reset. The vertical position stays the same.

Now the trick. During the display of the last line, the vertical sync kicks in. Roughly in the middle of the last line. During the vertical backporch, only the vertical position is reset. The horizontal position stays the same.

Because the horizontal lines are slanted a bit, that means the first line of the odd field starts in the middle of a horizontal line, and also at a vertical position that is half a line height offset from the even field.

That's all. No additional circuit. Just timing. If you want progressive scan instead, do the vertical sync at the beginning of the last line instead. That's within the range of the acceptable vertical sync.

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  • \$\begingroup\$ Aha! That's what the other answer means by a "half line"? And those lines are within the outer black region (what's the term? border?), and have no picture in, so this happens invisibly. \$\endgroup\$
    – pjc50
    Dec 10, 2021 at 12:55
  • \$\begingroup\$ .. so from the sending video card, this has the same horizontal and vertical timings as a non-interlaced mode, except it sends alternate lines and twice as many sync pulses as an equivalent-sized non interlaced mode? \$\endgroup\$
    – pjc50
    Dec 10, 2021 at 12:57
  • \$\begingroup\$ They are usually displayed in the shoulder of the CRT, yes. Some CRTs had a single dot in the middle of the top and bottom shoulder so the technician could align the first and last signal dot displayed to those real dots. \$\endgroup\$
    – Janka
    Dec 10, 2021 at 12:58
  • \$\begingroup\$ It sends just as many sync pulses. But for non-interlaced modes, both fields are identical and the resolution is halved. Or you need a video different mode. (You could of course send different fields and double the frame rate that way but that wasn't a thing back then.) \$\endgroup\$
    – Janka
    Dec 10, 2021 at 13:01
  • \$\begingroup\$ No there are no same timings between matching interlaced and progressive modes, as they differ with a factor of two, and the half-line that makes it interlaced. For example 1080i with 60 fields (30 frames) per second has half HSYNC rate and half pixel clock compared to 1080p at 60 fields (60 frames) per second, so interlaced mode has half the lines per VSYNC. For example, if TV cameras sent 480i, a retro home computer which does not interlace sent 240p and your CRT TV will understand it as they have same HSYNC rate and VSYNC rate (minus half line difference). \$\endgroup\$
    – Justme
    Dec 10, 2021 at 14:32
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The sync signals tell the monitor how to scan the signal, so the CRT monitor does not really know or care if it is an interlaced signal, it just scans the signal as it comes in.

In an interlaced signal, the frame, or two interlaced fields, is an odd integer amount of lines, which means that each field does not have an integer amount of lines as there is additional one half of a line per field.

In other words, every other field starts at the same time as the horizontal line and every other field starts in the middle of a horizontal line.

What this means in practice is that when the CRT beam is deflected from up to down at constant velocity for each field, after the lines of first field have been drawn, the drawing of second field starts half a line later in time, so the lines of the second field are drawn half a line down, between the lines of the first field.

The above describes the typical 2:1 interlacing scenario, but nothing prevents from using other interlacing scenarios such as 3:1 but they are just not practical.

In a progressive signal, each field is integer amount of lines, so the field always starts at the same time as the horizontal line.

  • SDTV 480i, 525 lines per frame, 262.5 lines per field
  • VGA 480p, 525 lines per frame, 525 lines per field
  • SDTV 576i, 625 lines per frame, 312.5 lines per field
  • HDTV 1080i, 1125 lines per frame, 562.5 lines per field
  • HDTV 1080p, 1125 lines per frame, 1125 lines per field
  • XGA 1024x768i, 817 lines per frame, 408.5 lines per field
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    \$\begingroup\$ What does "half a line" look like with regard to the hsync pulse timing? I'm having trouble envisaging that without a diagram. \$\endgroup\$
    – pjc50
    Dec 10, 2021 at 12:30
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    \$\begingroup\$ HSYNC timing is constant for each line so there is no half lines regarding the HSYNC timing. But there are half-lines regarding the VSYNC timing. The VSYNC pulse edge just happens exactly simultaneously with HSYNC pulse edge for every other field, and for the other field VSYNC pulse edge happens exactly midway between two HSYNC edges. \$\endgroup\$
    – Justme
    Dec 10, 2021 at 14:23

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