This comes up with digital working - flat panels, frame grabbers and the like. These systems that deal with interlace have to do the right thing with the scan line data to reconstruct full frames. On the other hand, analog CRTs just 'figure it out' (by design actually) and make the correct raster for interlace.
Say you're tasked with capturing video and so have to worry about this. The vertical sync vs. horizontal sync timing gives a clue to the capture system how to deal with the input.
- interlace: the 'second' field vsync starts in the middle of a line
- progressive: vsync always aligns with or near h-sync
From here: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/430417/dm8148-1080i-interlace-video-capture-with-vps_vip_fid_detect_mode_vsync-mode
Analog video with embedded sync (composite, component or sync-on-green RGB) requires a sync separator block that teases out H / V sync and blanking give you digital H and V signals as well as blank. V sync specifically is detected by looking at the composite sync equalization / serration pulses.
VGA with TTL sync already sends H and V separately, but nonetheless can also support interlace or progressive in the same way as embedded sync, by modifying V sync timing on the second field.
Either way, once you have the digital H, V and H blank signals, you test for V sync changing state during the active (non-blank) interval. A very simple way to do this is to clock the H blank signal period with the leading edge of V sync. If interlace is in use, first field will clock low, second field will clock high. If the field flip-flop never toggles (that is, V sync always falls during blank), congratulations, you have progressive.
A now-obsolete chip, the LM1881, did this for you. Link: https://www.ti.com/lit/ds/symlink/lm1881.pdf In addition to H and V sync, it outputs a toggling field signal, that won't toggle if progressive is in use. The circuit diagram shows the basic clocked-flop principle for field detect.