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How do I find the cut off frequency of a low pass filter? Consider the following part: https://www.analog.com/media/en/technical-documentation/data-sheets/1062fd.pdf

Edit: I have attached the schematic. What is it's cut-off frequency? enter image description here

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  • \$\begingroup\$ That's 5th order. How do you want to define the cut-off? \$\endgroup\$
    – jonk
    Dec 13, 2021 at 6:50
  • \$\begingroup\$ How can I define the cut-off? \$\endgroup\$
    – BlackHawk
    Dec 13, 2021 at 6:58
  • \$\begingroup\$ In many ways. Some folks like the -6 dB (voltage) cutoff definition. Others (me) prefer the phase inflection point. It gets complicated when you are higher than 2nd order, as there are many perspectives that then arrive. \$\endgroup\$
    – jonk
    Dec 13, 2021 at 7:06
  • \$\begingroup\$ Definition of a cut-off frequency is strictly governed by the corresponding application. Example: When you require that the signal within a passband of 1kHz must not be attenuated more tan 0.8 dB - then THIS is YOUR definition that has to be applied. \$\endgroup\$
    – LvW
    Dec 13, 2021 at 8:25
  • \$\begingroup\$ I have added the schematic. Please tell me its cut-off frequency. \$\endgroup\$
    – BlackHawk
    Dec 13, 2021 at 8:30

2 Answers 2

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You have the internal clock selected: -

enter image description here

That internal oscillator frequency can be anywhere between 15 kHz and 65 kHz and \$f_C\$ is defined as the 3 dB cut-off frequency so, \$f_C\$ will be one hundred times lower i.e. between 150 Hz and 650 Hz as per this: -

enter image description here

However, this only applies when the input resistor (R187 in your diagram) is 25.78 kΩ. Your resistor is 6.8 kΩ and this might make the actual 3 dB point slightly offset from that mentioned above due to causing a slight peak in the passband.

And finally, you should note this (red box) in your schematic: -

enter image description here

It is probably unacceptable to not have a capacitor fitted here (DNP = do not place). Ideally, you should decide what clock frequency you need from the internal oscillator and set it up on pin 5 so that you can tweak the cut-off frequency. From the data sheet: -

The COSC, Pin 5, can be used with an external capacitor, COSC, connected from Pin 5 to ground. If COSC is polarized it should be connected from Pin 5 to the negative supply, Pin 3. COSC lowers the internal oscillator frequency. If Pin 5 is floating, an internal 33pF capacitor plus the external interpin capacitance set the oscillator frequency around 140kHz with ±5V supply.

enter image description here

And this picture gives more information about making the internal clock adjustable AND defining what value \$C_{OSC}\$ should be: -

enter image description here

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  • \$\begingroup\$ So, is this schematic wrong in its entirety? \$\endgroup\$
    – BlackHawk
    Dec 13, 2021 at 9:59
  • \$\begingroup\$ There may be some (unknown to me) reasons why this schematic is perfectly valid for the designer's intention hence, I cannot say it is either wrong or right. Without a definition of the aim of the designer and the person drawing it, the schematic "is what it is". \$\endgroup\$
    – Andy aka
    Dec 13, 2021 at 10:02
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Wow, that's a hard data sheet to read, plus, there are errors which means this data sheet hasn't been proof read.

The corner frequency is: $$ f_o = {f_{clk} \over 100} $$ \$ f_{clk}\$ location is shown in the block diagram on page 5 of the data sheet

The clock generator oscillator runs at a frequency of \$ f_{osc} = {140kHz \left ( 33pF \over {33pF + Cosc} \right )}\$ (see page 6, "Cosc, Pin 5"). The internal oscillator frequency specification shows a wide variation of -20%, +50%, so the \$f_{osc}\$ equation is only approximate.

There is a divider between \$ f_{osc} \$ and \$ f_{clk}\$ which is set by the divider_ratio (pin 6).
V+ = \$ \div \$1
GND = \$ \div \$2
V- = \$ \div \$4 $$ f_{clk} = {f_{osc} \over n} $$ Where \$ n \$ is the divider_ratio setting of 1, 2, or 4. In your case, \$n\$ = 1.

One may expect the corner frequency in your schematic to be approximately 0.46 Hz if the oscillator capacitor is 100nF, or 1.4kHz if the capacitor isn't installed.

One should question the values of R187 and C148 in your schematic since it doesn't conform to the suggestions in the data sheet for either case of the oscillator capacitor.

From the graphs, the cutoff frequency looks like it's the -3dB definition.

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