symbols for ep3c5e144 and ep3c25e144 in Eagle

Question

I am using ep3c5e144 to design a PCB board. Sadly, in Eagle I cant find the exact library and symbol for this device, but only its near relative ep3c25e144.

I have some questions:

• How different is the pinning for ep3c5e144 and ep3c25e144? Can I reuse the symbols of ep3c25e144 for my design?
• Where can I find more about the information for ep3c25e144?

Sorry for such amateurish question, but I am a beginner. I have many confusions: for example, the VCC , should I connect them to 3.3V or 1.2V? There are 16 clocks, should I connect all of them?

Thank you so much for your help!

Answer 1

You can find Cyclone III documentation on this page.

In device handbook, look for "Table 1-2" (p.16). This table shows all available vertical migration options for Cyclone III family. "Vertical migration" means that when you design your board for one particular FPGA, you can replace this fpga with a higher density one (which has all the same pin layout etc.).

According to this table for E144 package EP3C5 and EP3C25 are compatible so you can use device symbol for EP3C5 instead of EP3C25.

Answer 2

FPGA design is really not for beginners because of its complexity and the amount of things to take into consideration. Especially because it's BGA with many pins and complex routing. I highly recommend you purchase or look at Altera reference designs.

With that said, you can reuse footprints if it's the same package. The actual pins depends on you and your pin assignment in Quartus II. For more information look at the Altera website for the datasheet. More importantly, take a look at development boards from Terasic or other companies to see how they connected everything.

The voltage you use on an I/O bank depends on what I/O voltage you need. That's up to you really, as long as you are within spec.

As for clocks, look at the reference designs. This depends greatly on your application. Not all clocks need to be connected.

As a final comment (not to sound too harsh) Eagle won't make it easy to route FPGAs. It'll be quite tedious (it already is with better software packages).