Logisim: timing problems setting register

Question

I'm having some problems understanding the timing behaviors I observe in Logisim. I've isolated some cases which illustrate the problem.

Say I have a register (1-bit, to keep it simple), which is being fed a logical 1 on its input D. Upon the clock the register is set to 1, as expected:

For this to work, the D input must already be receiving the logical 1 when the clock signal arrives. If, by using an N-type transistor, we only let the data line be high when the clock is high, then the register will no longer be correctly set, due to the delay introduced by the transistor:

Indeed, if we add two NOT gates to the clock line that is sufficient to delay the clock signal (relative to the data line) and make sure the D input receives the logical 1 on time again, allowing the register to be correctly set:

Of course, that is a horrible kludge and cannot be relied upon, since gate timings can vary due to component tolerances and other reasons. Still, so far so good, all of these behaviors made sense to me. What I don't understand is the following two cases.

I thought: if I put an N-type transistor in the clock line, to only let the clock signal pass after the data signal has passed its respective transistor, that should synchronize everything up. But it doesn't work:

It also doesn't work with a "Controlled Buffer" component:

Even more surprisingly, if I use a P-type transistor then the register is set, even though the register's clock input is floating, instead of set to high:

Can you please explain me these last two behaviors?

Answer 1

I've never used Logisim, but I have an idea of what it may be doing:

Some of your circuits lack pull-up/down at the clock input. It may be that it defaults to one (implicit weak pull-up). If that is the case, then a floating input is equivalent to a weak one.

With this in mind, in the circuit with the n-gate (or the controlled buffer, which I assume is a tri-state buffer) the register clock input never sees a zero (so it doesn't toggle). It can't because the n-gate is either propagating a one or disabled, in which case the floating register clock input defaults to weak one. Without a toggling register clock, data never gets clocked in, so it remains at the default zero.

Note that the order of assignments is:

1. input to n-gate
2. enable/disable n-gate simultaneous with register data input
3. output of n-gate simultaneous with register clock input.

In the last circuit with the p-gate the same order of events apply, but with different values. When the clock signal is zero then the p-gate is enabled due to the explicit pull-down, so the p-gate propagates the clock value of zero. When the clock signal transitions to one it disables the p-gate at the same time that it sets the register data input to one, and a unit delay later the register clock input goes floating (weak one), clocking in the current input, which we said is one.

So the first behavior is to never clock-in data, and the register output remains at zero. The second behavior is to only clock-in ones, so the register output goes to one and never returns to zero.

Answer 2

Short answer for new-commers : Logisim DOES NOT simulates signal level timing. Only state changes simulated via components.