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I am using TS30042-M033QFNR step-down voltage regulator.

The datasheet states to connect all the PGND pads together and then use vias to go to the 'general' GND plane on the back of the PCB.

In my design however, the 'general' GND plane is on the same side as the TS30042, so my question is, can I connect the PGND pads directly to the plane or do I have to separate them, and use a cluster of via to connect to a GND plane on the back (which I need anyway for thermal management) and then use stitching vias to re-connected to the main GND plane?

My understanding is that the two grounds have different purposes and thus must be connected only at one single point and thats the reason for the vias.

I am currently using the second alternative: enter image description here enter image description here enter image description here enter image description here

Edit: As requested my schematic and datasheet. enter image description here

Is this a good design or not?

Thanks

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  • \$\begingroup\$ Link the data sheet pdf file please. Please also show the exact schematic that matches your PCB layout diagram. Also, I'm confused about what are and what aren't your actual layout pictures. Some help needed here. \$\endgroup\$
    – Andy aka
    Dec 19, 2021 at 11:28
  • \$\begingroup\$ @Andyaka Added schematic and datasheet \$\endgroup\$
    – StefanoN
    Dec 19, 2021 at 11:37
  • \$\begingroup\$ I'd recommend rotating L1 90 deg counter-clockwise and C16, C17 clockwise. this would allow you to put C16, C17 much closer to D8, reducing output loop and feedback trace in half \$\endgroup\$
    – Maple
    Dec 19, 2021 at 14:50

1 Answer 1

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This is the current paths in the hot loop. I used red for toplayer and blue for bottom.

enter image description here

The output hot loop is similar:

enter image description here

There is no ground plane, so the paths for ground current are much longer than they need to be, which means high emissions, and possibly not working at all.

In addition, the thermal path from the thermal pad to copper on bottom layer is obstructed, so the chip will be hotter than necessary.

enter image description here

If you can put SMDs on both sides, the simplest is to keep a ground plane on top layer, and use the datasheet recommended layout on bottom layer.

If you have to put all SMDs on top, then a fat ground pour on the bottom to link the chip's ground thermal pad to the ground plane would be an option:

enter image description here

But this won't give proper cooling.

Normally when using SMDs, components and traces are on the same side, say top, otherwise you'd need vias everywhere. So there can be no ground plane on top because there are components and traces everywhere, it has to be on the other layer instead, usually bottom. So perhaps the root cause of this problem is that the "ground plane" is on the wrong side of the board, which means it's not a ground plane anymore, because there are traces and components in it, so it can't be reasonably unbroken.

If you have a mix of SMDs and thru hole, you can put the thru holes on one side and SMDs on the other side. That makes the board wave-solderable, and much easier to rework and prototype, because the large thru-hole parts don't get in the way when accessing SMDs.

You can also reduce capacitance on SW node by thinning some traces:

enter image description here

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  • \$\begingroup\$ Thanks! I was able to remove most traces from the bottom layer and shorten the loops by removing the isolated PGND plane + some rerouting on top, hopefully this is better. \$\endgroup\$
    – StefanoN
    Dec 19, 2021 at 16:03
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    \$\begingroup\$ Yeah it's much better. You could move some of these vias closer to the caps' GND pins. \$\endgroup\$
    – bobflux
    Dec 19, 2021 at 16:12

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