Before moving to understand the purpose of Hardware Description Language(HDL), we need to know what is HDL?

From wiki,

A hardware description language enables a precise, formal description of an electronic circuit that allows for the automated analysis and simulation of an electronic circuit.

The above description is too hard for me to understand so I will attach a more easy definition from Quora.

A hardware description language allows you to define a logic circuit as a kind of program. This allows you to define a circuit's behavior and also to simulate its operation.

So, from the above two definitions what I understood was, HDL is some kind of script where we define the behavior of different gates, and why we need that script is to create a simulation world where we can do some tests before moving to the hardware level. And this script can be written in two different popular languages. Verilog and VHDL.

Please, help me to correct my concept on the purpose of HDL if I am wrong.

N.B My background is in Computer Science & Engineering. I will appreciate it if you use simple words in your answer.

  • 1
    \$\begingroup\$ HDL is not all about simulation model of hardware. You can use software languages if it's only for simulation. HDL is in fact used for designing the actual hardware. Simulation is just one aspect of HDL. \$\endgroup\$
    – Mitu Raj
    Dec 24, 2021 at 14:40
  • 1
    \$\begingroup\$ Same reason you use a programming language instead of manually writing down millions of ones and zeros. It's a hell of a lot faster than placing millions or billions of transistors one at a time. \$\endgroup\$ Dec 24, 2021 at 17:35

5 Answers 5


Your interpretation is more or less correct at the first glance, but I think there are still some misunderstanding.

The term "script" you use isn't quite appropriate. The "script" term is typically used for languages that are interpreted by some software (e.g. a perl script is interpreted by the perl runtime, which is the software I'm talking about), it isn't usually used for languages that can be directly executed by the hardware (nobody use "script" to describe a C source code, which translates to machine code when compiled, which is directly executable by the target processor).

And that is probably a hint to the deeper misunderstanding you seem to have: the HDL code is not targeted to be interpreted by some runtime. The aim of HDL is to provide a way to describe hardware configurations of gates/flip-flops, and all kind of digital electronic blocks (you seem to have understood this), but the target can be more than just simulation. If the aim was just to simulate it, that wouldn't be very useful: you would write your HDL code, then simulate and test it, and then, when you want to make an actual chip with this very behavior... well, you do your design again with something else than HDL? What a waste of time, and the simulation you did was validating something that will have nothing to do with the final product.

HDL is typically used throughout the whole design from simulations to the final target chip, because it can sure be simulated (through some kind of interpreting runtime on a computer, as you indeed implied), but it can also be "compiled" (the term "synthesized" is actually used rather than "compiled" for HDL, but the principle is the same) into an actual chip design. The target can be FPGAs (generic chips containing lots of gates and flip-flops that can be dynamically configured in the way you want), or ASICs (actual custom chips that are engraved with the design you want). For FPGAs, synthesizing your HDL will produce some "bitstram" that you can load into the FPGA chip, and the chip will then physically behave as per your design. For ASICs, the synthesization will produce (very indirectly, but still) some masks used for silicon chip lithography.

That way, you can simulate, test, and go into production with the same design description, which avoids lots of mistakes and makes for a much faster design process. This is the whole point of HDL.

  • \$\begingroup\$ Hardware can directly execute HDL. Actually, the synthesizer does something here. It synthesizes or compiles HDL and produce bitstream which is 0s and 1s and load on FPGA. Why do we need to load HDL on FPGA in which we only defined some chips behavior? Because FPGA can be dynamically configured. And we actually configure FPGA by using HDL, right? \$\endgroup\$
    – F.C. Akhi
    Dec 24, 2021 at 16:17
  • \$\begingroup\$ Another point is, we write some gate configurations in HDL and the synthesizer synthesizes those configurations and produces bitstream. I actually write configurations but I didn't give any instructions that those configurations should implement on FPGA, right? Will it be automatically implemented on FPGA? Or, the synthesizer will do some extra job here, or do I need to do something more? \$\endgroup\$
    – F.C. Akhi
    Dec 24, 2021 at 16:18
  • \$\begingroup\$ @F.C.Akhi The fpga internally is a mess of lookup tables, registers and configurable routing, generally plus some special function blocks like rams, multipliers and PLLs, all of which are configured at startup by loading the bitstream. When writing HDL you usually find yourself copying 'instantiation templates' a lot of the time because while you can write with little concern for the reality of the fabric, that is not how you get high performance out of these parts. You have to constrain the design so that it meets timing, and sometimes that means placing specific bits of logic by hand. \$\endgroup\$
    – Dan Mills
    Dec 24, 2021 at 17:16
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    \$\begingroup\$ Hardware can not directly execute HDL. HDL is never "directly executed". An HDL can be synthesized into a low-level hardware description (which may be a bitstream that describes the switch settings in an FPGA, or a connection diagram for a sea-of-gates ASIC, or even a custom schematic). An HDL can be interpreted by a simulator on a computer. But an HDL is never "directly executed". \$\endgroup\$
    – TimWescott
    Dec 24, 2021 at 18:14
  • \$\begingroup\$ I would multiple upvote this if I could. As a programmer, the biggest problem I faced in using HDL/VHDL/Verilog was approaching it like a programming language, because it superficially looks like a scripting/programming language. And during simulation, that is true, but synthesis is where it all turns into hardware, and that's where experience as a programmer can cloud understanding. HDL statements are like a system of math equations, they don't execute in order: they only declare hardware to exist, all at the same time. There's no breakpoints or single step... \$\endgroup\$
    – MarkU
    Dec 24, 2021 at 23:19

HDL is what you specified it to be, a type of code that describes the circuit you are trying to create. The main difference of HDL in comparison to other coding languages you already may know, such as C or python, is that the HDL is written such that the execution done in parallel, as is done in a real circuit, so the designer must take care in specifying which parts of the circuit happen in parallel (combinational logic) and which parts happen one after another (sequential logic). Within the HDL, the behavior of low-level gates can be specified, allowing the designer very specific control over the exact circuitry desired. High level design can also be specified, allowing the designer to build larger blocks and modules, such as memory arrays, ALUs, etc.

Once the behavior of the circuit is specified using the HDL, the design is synthesized. This means that the description of the circuit is taken and placed into actual circuit elements, such as logic gates. The synthesis is holistic, and elements from the behavioral description are inferred by the synthesis program. Once the circuit is implemented (defined in its hardware elements), it can be simulated in order to debug, fabricated into a chip, or ran on an FPGA.

  • \$\begingroup\$ If design synthesized means "the description of the circuit is taken and placed into actual circuit elements", then why do we need to place HDL on circuits? I don't know if my question is silly or not. Say, an AND gate chip is designed in a way that it will give 1 as o/p when both of the inputs are 1 otherwise 0. Why do we need to write its behavior in human language and again placing on this chip? Yes, we need to write descriptions in human language so that we can read later and remind behavior of AND gate. But, why er placing on AND gate, it is designed to give o/p as specified, right? \$\endgroup\$
    – F.C. Akhi
    Dec 24, 2021 at 15:08
  • \$\begingroup\$ @F.C.Akhi: Please edit your question with this additional query. It seems to be part of the answer you're looking for, and StackExchange wants your question to be complete, not broken into bits and buried in the comments. \$\endgroup\$
    – TimWescott
    Dec 24, 2021 at 18:16
  • 1
    \$\begingroup\$ @F.C.Akhi: The HDL is not "placed" onto the circuits. The HDL describes the behavior of the circuit to be created. The synthesis program understands this behavior and models it using gates and other circuitry. Specifying an AND gate within the HDL will cause the synthesis program to use an AND gate. However, more sophisticated circuits, such as a RAM, can be implemented in many ways, and our description of how our implementation should be, as given in the HDL, is used by the synthesis program to determine in what way and using what components the circuit should be implemented. \$\endgroup\$
    – md-raz
    Dec 24, 2021 at 20:18

Here is a schematic for a one-bit full adder with carry in (it's figure 5.3, here):

enter image description here

If you want to make that into a 16-bit adder, you'd need to replicate that 16 times. That would take up all of a letter-sized sheet of paper, if you stick to reasonably-sized elements.

  • It would take an expert to look at the schematic and infer the function.
  • If you're doing synchronous design, where the input comes from a set of registers or goes to a set of registers, those would have to be included.
  • If you want to change to a different way of implementing the add, every schematic element would have to be changed.
  • If you were using an FPGA that includes DSP blocks, the schematic would have to be changed to specifically call out the DSP blocks.

Here's a generic-HDL way of specifying a 16-bit adder, while latching into a register (I haven't done FPGA design much recently, so Verilog and VHDL are mixed up in my head - just trust me here, or if someone reading this is more facile than I am, they can edit my answer with actual HDL):

  • Define a module that takes two 16-bit wide inputs called A and B, a clock, and has a 16-bit wide output called C.
  • Somewhere in the code, say "on the rising edge of the clock, C = A + B, and use the form that implies the answer should be latched.

A simple "add two numbers module" would be about 10 lines (and trivial enough that you probably won't find it). People who don't know what it does would see that the only substantive line it it was C = A + B and think "gosh, I bet two numbers are being added, here".

If it is properly written, that code can be:

  • simulated behaviorally to make sure the logic is right
  • Synthesized for any brand of FPGA, regardless of the implementation details
  • Synthesized for any process of ASIC, regardless of the implementation details
  • Synthesized (if I'm correct about what open-source software is out there) for 7400-series logic on a board

That means -- if it's properly written -- that you can take stuff that module into a library of modules, and you can use it under any technology under the sun. You can sell it, you can share it open source, you can keep it as a company resource and no one needs to worry about the underlying schematic (unless it doesn't work).

In fact, the normal design flow for a new application that's going to end up on an ASIC is to first run it in simulation, then get it running on one or more FPGAs, and only then, when you have proved out the logic, actually start designing your ASIC. All of this is done using some HDL or another.


In order to describe hardware, you need a hardware description language...

The whole point is to synthetize it into hardware, for example in a FPGA or in a hard chip, and the language is how you tell the synthesis tools what to do. It's just not possible to draw schematics for modern chips with millions/billions of transistors.

  • \$\begingroup\$ I didn't understand what you meant by synthesizing into hardware:( \$\endgroup\$
    – F.C. Akhi
    Dec 24, 2021 at 14:45
  • \$\begingroup\$ Synthesis means the software compiles the HDL into actual hardware (netlists, schematics, etc) that can be used to implement the circuit in a programmable chip like a FPGA, or to make a real chip. \$\endgroup\$
    – bobflux
    Dec 24, 2021 at 15:09

So, from the above two definitions what I understood was, HDL is some kind of script where we define the behavior of different gates,

Yes, it can, but we can also use it at a much higher level, for instance to define the behaviour of adders, multipliers etc where we let the subsequent tools figure out how to implement the logic for them.

and why we need that script is to create a simulation world where we can do some tests before moving to the hardware level.

We need the script to define the behaviour of a design in a standard, high level, machine (and human) readable way, so that we can use it as input to downstream programs. Simulation is one thing, another is to use it as an input to a synthesis program that implements our design in hardware, whether FPGA or ASIC. It needs to be transportable between different vendors' tools (graphical was very popular early on when designs were small, but file formats for graphical representation were just too difficult to standardise and move between vendors, and it didn't scale well to large designs).

And this script can be written in two different popular languages. Verilog and VHDL.

Those are the two most popular in existence today.

  • \$\begingroup\$ I didn't understand the downstream programs and synthesis program you mentioned above. Could you give a simple example? What I understood from your answer is, HDL is not only a script or documentation on chips and simulation of ICs. Its other purpose is to define behavior in human-readable language and can be transportable between vendors. \$\endgroup\$
    – F.C. Akhi
    Dec 24, 2021 at 14:57
  • \$\begingroup\$ @F.C.Akhi Humans can't design a 10 million gate IC, it's just too big. So machines have to do it. So you need a high level language that tells them what to design. Think of HDL being synthesised to hardware as the same flow as a compiled language being compiled to an executable. Humans wouldn't be able to write an operating system of today's size in assembler, so it's written by a compiler, that understands a high level language as input. Neither assembler language, nor sketching AND gates graphically, can scale to the size of today's designs. \$\endgroup\$
    – Neil_UK
    Dec 24, 2021 at 15:51
  • \$\begingroup\$ @F.C.Akhi Perhaps your question is this - 'If HDL is the answer, what is the question'? The question is how do you design very large logic circuits, without being dependent on a single vendor. If you needed to move a design between (say) Xilinx and Altera, you're not going to want to re-design your chip using the other guys' tools. Both vendors can read HDL files, and synthesise their own version of the logic from that. Both will behave the same, even though both are implemented in very different logic cells within their FPGAs. Look up FPGAs and ASICs on wikipedia. \$\endgroup\$
    – Neil_UK
    Dec 24, 2021 at 15:57

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