Your interpretation is more or less correct at the first glance, but I think there are still some misunderstanding.
The term "script" you use isn't quite appropriate. The "script" term is typically used for languages that are interpreted by some software (e.g. a perl script is interpreted by the perl runtime, which is the software I'm talking about), it isn't usually used for languages that can be directly executed by the hardware (nobody use "script" to describe a C source code, which translates to machine code when compiled, which is directly executable by the target processor).
And that is probably a hint to the deeper misunderstanding you seem to have: the HDL code is not targeted to be interpreted by some runtime. The aim of HDL is to provide a way to describe hardware configurations of gates/flip-flops, and all kind of digital electronic blocks (you seem to have understood this), but the target can be more than just simulation. If the aim was just to simulate it, that wouldn't be very useful: you would write your HDL code, then simulate and test it, and then, when you want to make an actual chip with this very behavior... well, you do your design again with something else than HDL? What a waste of time, and the simulation you did was validating something that will have nothing to do with the final product.
HDL is typically used throughout the whole design from simulations to the final target chip, because it can sure be simulated (through some kind of interpreting runtime on a computer, as you indeed implied), but it can also be "compiled" (the term "synthesized" is actually used rather than "compiled" for HDL, but the principle is the same) into an actual chip design. The target can be FPGAs (generic chips containing lots of gates and flip-flops that can be dynamically configured in the way you want), or ASICs (actual custom chips that are engraved with the design you want). For FPGAs, synthesizing your HDL will produce some "bitstram" that you can load into the FPGA chip, and the chip will then physically behave as per your design. For ASICs, the synthesization will produce (very indirectly, but still) some masks used for silicon chip lithography.
That way, you can simulate, test, and go into production with the same design description, which avoids lots of mistakes and makes for a much faster design process. This is the whole point of HDL.