# VHDL : "wait on" vs sensitivity list

I read that a process with a sensitivity list is equivalent to a process with wait-on statement at the end.

Why does "wait on" statement have to be at the end of the process to behave the same as the process with the sensitivity list.

Example 1:

process is
begin
if Sig1 = Sig2 then
report "test";
end if;

wait on Sig1, Sig2;
end process;


Example 2:

process is
begin
wait on Sig1, Sig2;

if Sig1 = Sig2 then
report "test";
end if;
end process;


At the first example : the if statement will be executed once then will wait for Sig1 or Sig2 to change but why? I thought that it should wait for Sig1 or Sig2 to change at first so that it can execute the if statement (I thought that in this case like shown in Example 2, it will behave like a process with a sensitivity list).

• Because that's the way process semantics are defined. Every process runs ONCE in the first delta cycle. Example 2 will sit at the "wait", example 1 will run then wait. Only example 1 matches the semantics of the sensitivity list. Dec 25, 2021 at 13:58
• @user_1818839 doesn't the sensitivity list wait for its signals to change then enters its process ? Dec 25, 2021 at 17:20

The wait statement will only be equivalent to a process with a sensitivity list if the wait statement is given immediately before the end process statement.

See Note 1 of section 9.2 of the IEEE VHDL standard given here

The rules in 9.2 imply that a process that has an explicit sensitivity list always has exactly one (implicit) wait statement in it, and that wait statement appears at the end of the sequence of statements in the process statement part. Thus, a process with a sensitivity list always waits at the end of its statement part; any event on a signal named in the sensitivity list will cause such a process to execute from the beginning of its statement part down to the end, where it will wait again. Such a process executes once through at the beginning of simulation, suspending for the first time when it executes the implicit wait statement.

In short, this is the specification agreed upon, and that's why the wait statement must be on the end.

A 'wait on' statement at the end of a process ensures that the process is carried out once at the start of simulation, before waiting for the signals it is sensitive to.

Superficially, a process with a sensitivity list is equivalent to a process with a a 'wait on' statement as its final line.

An important difference, though, is that a process with a sensitivity list cannot contain any 'wait' statements, whereas a process without a sensitivity list can.

This distinction is relevant for simulation only, such as in testbenches and models. It does not affect synthesisable VHDL as the wait statements beyond those for sensitivity cannot be synthesised.

For example, a simulation model can use a non-list process to implement propagation delays, such as in this basic and incomplete example:

  pModelSPI : process is
begin

if falling_edge(spiCSN) then
bitCtr   <=  0;

elsif rising_edge(spiSCLK) then
bitCtr   <=  bitCtr + 1;
rxSR     <=  rxSR( 6 downto  0) & spiMOSI;

elsif falling_edge(spiSCLK) then
wait for 5 ns;
txSR     <=  txSR( 6 downto  0) & '0';
spiMISO  <=  txSR( 7);

elsif rising_edge(spiCSN) then
spiMISO  <=  'Z';

end if;

wait on spiCSN, spiSCLK;

end process pModelSPI;