How to constrain a source-synchronous FPGA input?

Question

I have a source-synchronous input to my FPGA (an Intel Cyclone 10 GX 10CX085), coming from an external chip whose datasheet gives the following information:

• f_max = 300 MHz (single data rate)
• t_setup = 0.4 ns
• t_hold = 0.5 ns

Using an oscilloscope, I can see the data is "center-aligned" (such that the data values are stable near the rising edge of the clock).

I have stripped my whole design down to two flip-flops and I still struggle to meet timing, even if I heavily relax the timing constraints. The whole Quartus project can be downloaded from here.

By closely following Intel's free training course, I understand that for best timing performance I should instantiate a PLL (specifically, an IOPLL configured in "source synchronous" mode) and my timing constraints should be defined like this:

# Define input clock parameters
set period 3.333
set tsu 0.4
set th 0.5

# Define input delays
set half_period [expr $period/2]
set in_max_dly [expr $half_period - $tsu]
set in_min_dly [expr $th - $half_period]

# Create virtual launch clock
create_clock -name virtual_clock -period $period

# Create physical base clock (phase shifted by 180 degrees) on FPGA pin
create_clock -name Clk -period $period -waveform "$half_period $period" [get_ports Clk]

# Create generated clocks on the PLL outputs
derive_pll_clocks

# Set input delay constraints
set_input_delay -clock [get_clocks virtual_clock] -max $in_max_dly [get_ports InData*]
set_input_delay -clock [get_clocks virtual_clock] -min $in_min_dly [get_ports InData*]

This failed timing catastrophically, so I tried relaxing to a 10 MHz clock with an extremely generous t_hold = 25 ns:

# Define input clock parameters
set period 100
set tsu 0.4
set th 25

This also failed timing. However, if I manually adjust the phase of the PLL (to basically anything sufficiently larger than zero) then timing is of course met comfortably at 10 MHz:

This leaves me very confused about the following:

• Are my requirements (300 MHz, 0.5 ns, 0.4 ns) feasible with this device?
  • If so, then how? (Timing contraints, PLL configuration, etc).
  • If not, then what performance is possible? (I can't see this information anywhere in the FPGA documentation).

Many thanks in advance for any help!

Answer 1

Your exact timing requirements from the source seems a bit unclear?

tsetup = 0.4 ns. thold = 0.5 ns.

If you by these numbers really mean to say that the input signal is valid only during a 0.9ns window around the edge of the clock, then there is no way you can do this on an FPGA using just the phase shift of an IOPLL. You need a valid window of several nanoseconds for that to work. Hard to say what the exact limit is. It is essentially the sum of the IO and routing delay uncertainty, and PLL delay uncertainty

You need dedicated hardware to make it work with a valid window of only 0.9ns, and you are in luck: The Cyclone 10 has such hardware capability. It is called "phylite" and is used for high speed source synchronous interfaces such as DDR3.

Look it up in the cyclone 10 datasheets. It should do the job.

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EDIT: Thanks - I have looked it up and, after a protracted battle with atrocious documentation and toolchain bugs, the details of a working PHY Lite solution can be found here:

https://electronics.stackexchange.com/a/614796/220993