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I have a nanocrystalline center-tapped transformer with 2 turns at the secondary and 17 turns at the primary. There are 4 windings at the secondary as each leg of the transformer is parallelized with 2 windings. It looks like this:

schematic

simulate this circuit – Schematic created using CircuitLab

Do not take into account the inductance value; it is wrong.

This transformer is inserted into a full-bridge forward converter.

My problem is the following:

When I apply a voltage across the primary and let open the secondary, which means that no current other than the magnetizing current can flow at the primary, the transformer does not saturate even at the maximum duty cycle. According to the formula:

$$B_{max} = \frac{V_{in}\cdot T_{on}}{N_p\cdot A_e}$$

Where Ton is the time during which the MOSFET is ON, Vin is the input voltage, Np is the number of turns at the primary, and Ae is the magnetic section.

According to the formula and what I have in theory, the transformer should not saturate.

Nevertheless, when I apply a current at the secondary, even very low as regards of the current section, I should say even for a very low current density as the current at the primary jumps to 5 A but it can go up to 75 A, the transformer is saturating. I hear a noise and I can see, using a current probe, that the current has a saturating waveform. But what is pretty strange is that it is saturating only on one side.

enter image description here

(I deactivated the voltage regulation of the controller in order to always have a full duty cycle as due to the saturation, the controller could stop the ON time before the maximum ON time, and it will have the tendency to reduce the problem. Nevertheless, it is not really safe to keep this problem and my equipement has already been destroyed during testing and I think it is coming from this problem.)

It probably means that when I apply a current, I am able to displace the average point on the BH-curve.

My converter looks like this :

enter image description here

And the BH curve is the following :

enter image description here

And what I think is happening but I do not know why:

enter image description here

I was thinking at the beginning my duty-cycle waveform was set without a soft start, I mean when I start to set Vin across the transformer during Ton and then I apply minus Vin during Ton I will displace my average point from the center to the corresponding exciting magnetic field H, so the duty cycle must increase gradually in order to let the avarage magnetic field go to 0 ideally.

I also tried to increase Vin with the secondary open, to see if I had some margin between the saturation and my operating point, and I do have some margin! I am not able to saturate it; I will damage my capacitors before saturating it, so there is really something happening when I am applying current.

If you have some ideas, please let me know.

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  • \$\begingroup\$ What's the expected maximum primary current? I've dealt with the exact same problem in the past. If the current is at most a couple dozen amps, a few cheap coupling capacitors might help. \$\endgroup\$ Dec 27 '21 at 20:52
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    \$\begingroup\$ Show the precise waveform of the primary current plrase. \$\endgroup\$
    – Andy aka
    Dec 27 '21 at 21:11
  • \$\begingroup\$ @JonathanS. the expected maximum primary current when the secondary is not open is 75 amperes. I already have decoupling capacitors but It could be not enough ... You mean that the input voltage could be not perfectly equal at each on time ? Sometimes I apply Vin and the next time I aplly "-Vin + delta". I forgot to say that the equipement is 3 phase equipement. \$\endgroup\$
    – Jess
    Dec 28 '21 at 8:37
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    \$\begingroup\$ It's not quite clear to me yet what you mean by "delaying the time". You will either need some kind of active DC bias suppression or a series capacitor. Take a look at this: mdpi.com/2079-9292/10/4/428/pdf \$\endgroup\$ Dec 28 '21 at 13:38
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    \$\begingroup\$ With nothing on the primary to detect and maintain equal positive and negative Vt, you are left with series capacitor to block the DC offset. \$\endgroup\$
    – winny
    Dec 28 '21 at 18:29

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