0
\$\begingroup\$

I'm in the process of designing my own lab power supply. During my research I came across a design from electronics-lab.com that seems to be very popular for DIY adjustable power supplies (here is a forum topic with over 2000 replies!). This is the schematic I'm talking about:

electronics-lab.com schematic

There are a few variations floating around, but as far as I can tell, this is its origin.

According to numerous posts on various forums, this circuit seems to have a few problems with stability and transient and turn-on and -off behaviour. There have been many efforts to alleviate those, but to me even the basic circuit seems overly complicated with its ground above the current sense resistor, the high-voltage op-amps and the weird negative rail generation.

I was initially going in the direction of a simpler architecture, seen in this image (this is not supposed to be a full schematic but just to show the topology; e.g. analog supply stuff, filters for loop stabilization and parallel pass transistors are missing):

schematic

simulate this circuit – Schematic created using CircuitLab

The op-amps in this circuit can be low-voltage types. In case I deem a negative rail necessary so that OA2 can pull the voltage setpoint to 0, I'd go for a readily available charge pump IC.

Now to my question: what advantages does the electronics-lab circuit have over other topologies such the one I drew? Does it inherently perform better in some areas? Or does its popularity only stem from its "momentum"?

\$\endgroup\$
12
  • \$\begingroup\$ Your topology is identical to the original circuit; the only difference is the high-side shunt resistor which requires a high-side current sense IC. The PNP pass transistor will simply not work (too much voltage gain). The original circuit also does actually use a charge pump to generate the negative rail (D5, D6, C2, C3). Both topologies will oscillate quite happily in current regulation mode. U1 generates what you called "Vref" in your circuit, you'll need that too. \$\endgroup\$ Dec 28, 2021 at 20:12
  • \$\begingroup\$ @JonathanS. I agree that the topologies aren't too far apart. However, if I'm not mistaken, the original circuit requires op-amps with a very large supply voltage range. Also, the supply current of U1 and its accompanying circuitry is routed through the shunt resistor which makes the current measurement imprecise ("ground above the current sense resistor"). It's not a normal low-side shunt with differential amp. You are right about the negative rail charge pump. \$\endgroup\$
    – Max Klein
    Dec 28, 2021 at 20:29
  • \$\begingroup\$ @JonathanS. Also, if I may ask, why do you say that these topologies will oscillate in constant current mode? Is this an affect of the diode (D5 in my drawing)? And what can I do about it/are there topologies that aren't affected by this? \$\endgroup\$
    – Max Klein
    Dec 28, 2021 at 20:31
  • 1
    \$\begingroup\$ The reason for the oscillation is that the circuit's loop gain will become very high when it's delivering a constant current into a low resistance (a short / large capacitor). A low-impedance load turns the output transistor into a common-emitter amplifier. (In your topology it already is a CE amplifier even in constant voltage mode.) This adds so much loop gain that the OpAmp becomes unstable. See my recent answer here about a similar circuit: electronics.stackexchange.com/a/602079/166183 You need to add a damping network to the output and compensate the circuit very carefully. \$\endgroup\$ Dec 28, 2021 at 20:44
  • 1
    \$\begingroup\$ I worked on fixing some of the problems of the Electronics-Lab project that was a copy of an older one. Now Chinese companies have copied the original defective circuit. Your circuit needs to have a negative supply so that your diode D5 can prevent a fire when the circuit's output current is too high. I agree that your Q1 must be a follower with a gain of 1 to avoid oscillation and the opamps must be high voltage ones. \$\endgroup\$
    – Audioguru
    Dec 28, 2021 at 22:18

1 Answer 1

0
\$\begingroup\$

EDIT : "other" example of power supply. Not completely tested.

Current limiting topology. Low voltage op-amp used.

enter image description here

Post useful

Using a power schematic like this one, a general op-amp may be used.

enter image description here

For reference, TRANsient analysis ...

enter image description here

An AC Analysis ...

enter image description here

\$\endgroup\$
2
  • \$\begingroup\$ According to the comments of Jonathan S. and Audioguru below the question, stages with high gain should be avoided unless I have experience in compensating the control loop. Because of that I already discarded the idea of using low-voltage op-amps. If I'm interpreting the first graph correctly, this circuit has a voltage gain of about 100. Does it alleviate the stability problems in some other way? \$\endgroup\$
    – Max Klein
    Dec 29, 2021 at 21:04
  • \$\begingroup\$ Right about the gain of almost 40 dB. This gain is made by the two transistors Q3 and Q4, which are quasi CC topology because of R6 and R8. It is the reason why I also made a simulation (TRAN and AC) to see the response of this "power amplifier". The goal is to have a "current drive" of Q2 which is at high voltage (voltage gain may be reduced). Transistors used are a little "obsolete", so must be changed for new ones. A differential pair may be used for the stages Q3 and Q4, which would be "better", and "probably" fewer stability problems. \$\endgroup\$
    – Antonio51
    Dec 29, 2021 at 21:54

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.