# Common emitter amplifier - calculate Q-point?

I am currently studying the common emitter amplifier and I am getting some nasty clipping in the output. So what I am trying to do is to figure out how I can calculate the highest and lowest output voltage (U_CE). My goal is to put the Q-point in the middle of it to have a maximum amplitude symmetrical output signal.

This is my circuit. Its very basic. I use an ideal AC-source with a DC-Offset to set the DC-Bias of UBE. The transistor uses a constant Beta = hFE = 100.

So as far as I understand the transistor cycles between cut-off region, active region and close to saturation.

When the input signal amplitude (sine wave, UBE) has a negative peak, the transistor should be in the cut-off region. Therefore I assume IC = 0A and UCE = 20V.

When the input signal amplitude has positive peak, the transistor is on the edge of saturation. Therefore UBC = 0 and UCE = UBE_max.

So now I put the Q-Point in the middle: UCE_Q = (20V+UBE_max) / 2. I choose my IC = 100mA. Therefore collector resistor RC=103ohm (approximately using UBE_MAX = 0.7V)

Doing so I get pretty bad clipping on the positive input half waves. What am I doing wrong? I understand when the input signal amplitude is too big I get clipping. But in this case the output signal is clipped almost for a whole of the positive input half wave. This leads to the conclusion that the Q-point is not in the middle of the active region. But why?

• If you set the amplitude of the AC portion of the input signal to a very small value (say nanovolts), leaving just the DC offset, you can see exactly how your large-signal bias is working (or not working). Dec 29, 2021 at 0:56
• I know and I have already set the AC part to 0 to see the Q point. And it is what I calculated. It just seems that it isnt in the middle of the active region. So my formulas must be off somewhere I assume. Dec 29, 2021 at 1:18
• With the AC part of the input set to 0, what is the output voltage? Dec 29, 2021 at 1:45
• The output voltage with AC=0 is UCE=9.57V. IB=1.013mA, IC=101.259mA, VBE=715mV, VBC around -9V Dec 29, 2021 at 2:20
• My goal is to put the Q-point in the middle of it to have a maximum amplitude symmetrical output signal. then abandon that circuit immediately and use one with a tad more sophistication. Dec 29, 2021 at 6:59

The transistor does not have constant beta. The beta reduces as the collector current reduces which causes the severe distortion where the tops of the waveform are squashed and are not clipping. You need to add negative feedback to reduce the distortion.

• Owww ok. So the amplitude at the input is too high and the small signal beta just doesnt cut it anymore. So my voltage amplification is too small I assume! So either I use R_E as feedback to be less dependent on the beta or I have to increase my voltage amplification to get away with a small ampliude at the input? Dec 29, 2021 at 13:22

You can't easily set the bias point in this circuit.

Basically because the gain of the transistor is so high, minor errors in the choice of base voltage (which is around 0.7 V, but not precisely that, the collector current (and therefore V in this circuit) will have wide variations.

The appropriate DC value of base V is usually generated using negative feedback around the transistor. This also has the effect of reducing the gain (which may be unwanted), and also of linearizing it (making it constant which is generally desirable).

If you still want a large gain, it will require more components to get a large and stable gain.

An emitter resistor will generate negative feedback (and effectively reducing the gain) and also simplify setting the Q point. With an emitter R, the overall gain will be about -Rcollector/Remitter.

• My simulation shows a voltage gain of 74 times and each transistor will have a different hFE and a different Vbe. You need plenty of AC and DC negative feedback by adding a series input resistor and a bias resistor to the collector, or an emitter resistor to ground. Dec 30, 2021 at 18:26