# Test_bench in Verilog using Task

I have written testbench in verilog. All the test cases define in task works independently well but when I try to run both task then it give proper output for 1st task in task_operation but not for other task. The stimulus remain there for another task also. I want to use input in task as locally instead of globally define. How should I define input in argument in task so that input should be given independently?

module tb();
reg data_i_t;
reg dcsel_t;
reg clk ;
reg reset_t;
reg reset;
reg xlat_t;

initial begin
#2 reset =0;
#100000 $finish; end task task_operation(); begin exp_case_2a(data_i_t,reset_t,read_t,dcsel_t,xlat_t,data_out_1); exp_case_2b(data_i_t,reset_t,read_t,dcsel_t,xlat_t,data_out_1); end endtask task exp_case_2a; input data_i; input reset; input read; input dcsel; input xlat; output reg [47:0] data_o; begin repeat(47) begin @(posedge clk) data_i = 1; reset = 0; read = 1; dcsel = 0; xlat = 1; data_o = Data_out; end #5250 compare_data_2(data_out_tb); end endtask task exp_case_2b input data_i; input reset; input read; input dcsel; input xlat; output reg [47:0] data_o; begin repeat(47)begin @(posedge clk) data_i = 1; reset = 0; read = 0; dcsel = 0; xlat = 1; data_o = Data_out; end #5250 compare_data_2(data_out_tb); end endtask /* ........... SCORE-BOARD.............. task compare_data_2; input [47:0] exp_data; begin if(exp_data == comp_data_1 ) begin INFO("TEST PASSSED",$time);
$display(" exp_data : %h ",exp_data); end else begin `ERROR("TEST FAILED",$time);
$display(" exp_data : %h ",exp_data); end end endtask ## 1 Answer It would be helpful if you could clarify this statement : How should I define input in argument in task so that input should be given independently? A task defined as: task display_redux input [31:0] a_number; begin$display("display_redux was sent : %d", a_number);
end

Can be called with :

display_redux(20);
integer ii = 6;
display_redux(ii);

To me the input here is independent from anything else, and you can not assign value to the input so it does not have side effects from of modifying inputs from where it was called.

input data_i;
input reset;
input dcsel;
input xlat;
output reg [47:0] data_o;
begin
repeat(47)begin @(posedge clk)
data_i = 1;
reset  = 0;
dcsel  = 0;
xlat   = 1;
data_o = Data_out;
end
#5250 compare_data_2(data_out_tb);
end

Youve declared many inputs which you are not driving when you call it with exp_case_2b(data_out). You have defined inputs then are trying to drive values on to them. You need these to be regs and not inputs so they are local to the task. Or not defined at all and use hierarchical references to the top level reset, aka tb.reset = 0;.

I think this might have been what you were trying todo:

input      [47:0] data_i;
output reg [47:0] data_o;
begin
repeat(47)begin @(posedge clk)
data_i = 1;
reset  = 0;