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I have a PCB that when I run a design rule check in KiCad I am getting an error that an IC's earth pins are unconnected to a via which is also connected to earth. I don't get these errors a lot so I was hoping to verify that this was a software problem and not a PCB design error.

Both the red and green planes shown on the pcb below are ground planes. All vias shown are connected from the front copper layer to the back copper layer. Each via upon close examination says "earth".

How can I get rid of this error?

pic1 pic2 pic3 error

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  • \$\begingroup\$ Does the problem go away if you place a track from the IC pads to the vias (or just to the copper plane)? \$\endgroup\$
    – Mat
    Dec 31, 2021 at 7:35

2 Answers 2

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The thermal relief pattern around those pins indicate that the ICs pins are too close to each other for the set clearance. There is a visible bridge but it does not touch the center of the pin so the connection algo will declear it to be not connected IIRC. You can verify that by moving the IC away after the poly was filled. Solution: set the clearance/thermal relief settings of the polygon to a value which allow a proper connection.

Alternatively you can use the approach suggested by @Mat - use an explicit track instead of the polygon filling to make the connection.

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There is a funny quirk with how Kicad determines a pin is connected w.r.t a zone and it has to be connected on the short-side of the pin.

With the thermal relief setting enabled AND the Thermal relief gap setting as it is AND the net clearance rule it means the connection cannot be made on the short-side and only on the long-edge.

Recommendation: reduce the Thermal relief gap to that of the thermal relief

Also v6 was release just before Christmas ( https://www.kicad.org/download/windows/ ) so consider updating, v6 has soo many improvements its <3 (but backup a v5.1 version just in case)

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