Here's the question: enter image description here

Each full adder has 2 AND gates 2 XOR and 1 OR gate so carry propagation delay for each full adder should be 80 ns by the data provided and as there are 4 full adders, so shouldn't the answer be 80 * 4, 320 ns? I am new to learning digital electronics. Please help me out and explain it as for a beginner. Although I am well versed with basics so you can save some of the but obvious terms and explanation.

  • 1
    \$\begingroup\$ Why do you think that each adder has 80 ns propagation delay? Did you just sum the delays of each gate? Remember that things happen in parallel as well, it's not that all the signals goes through every gate in a sequence. The same applies for the full 4-bit adder. You only need to consider the slowest path of one signal. Calculate how long it takes for Z1 to be stable, then how long it takes from that until Z2 is stable etc. \$\endgroup\$
    – Klas-Kenny
    Jan 1, 2022 at 7:22
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    \$\begingroup\$ Simply adding up the prop delay of ALL the gates in the FA will give you an upper bound without doing detailed work, but you need to do the detailed work, to add up the gates on the relevant paths. For instance Zin to Zout has an AND and an OR gate, for a carry delay of 25 nS. Do the same for each input->output pair in each FA, then do the same for the 4 bit adder. Then add up the total prop delay only for the inputs that change. \$\endgroup\$
    – Neil_UK
    Jan 1, 2022 at 7:27

1 Answer 1


You have to check the longest path through the design. In this case it involves the carry, because that goes through all the adders.

enter image description here

The question isn't clear whether the output that is considered in the question includes the carry output of the last adder, or just its 1-bit result output. So let's do both.

Two paths in the first adder, from inputs to carry output: 1 AND, 1 OR (blue, 25ns) XOR, AND, OR (purple, 45ns). We take the longest one and ignore the path from carry input, which is shorter.

enter image description here

Then the carry output of the first adder ripples through the next two ones, combining with the inputs to produce the next carry output.

enter image description here

There's a subtlety here. Do the two gates on the left (AND, XOR) count, as their output signal combines with the carry in the AND gate indicated by the arrow, to make the output carry?

If we consider that all inputs are presented at the same time, then by the time the carry from the previous adder arrives, the two gates on the left will have done its job already. So the path that matters for carry propagation is only through the bottom AND, OR gates (25ns).

Note this is hardware, so all paths that are parallel, run in parallel, so their times don't add up. Only the longest time counts. The first adder delivers its output bit quickly, but meanwhile the carry is still propagating through the other adders.

In the last adder, the delay from inputs (X,Y,carry) to output is 2 XOR (40ns). But the two bit inputs and the XOR gate on the top left have settled long before the carry arrives, which means, as previously, the top left XOR doesn't count.

enter image description here

So if we're only interested in propagation time from inputs to outputs and not carry, the total delay is (1 AND, 1 OR)*3 + 2 XOR. If we're interested in propagation to the carry output, then (1 AND, 1 OR)*4 + 1 XOR. So we take the longest of the two.

That's the answer to "what's the maximum propagation delay of this adder" which would be a useful thing to know about the adder if you want to use it to add two arbitrary numbers.

But this is not the question being asked! If you read the fine print, you'll notice that all inputs are initially zero, and then the inputs toggle to 1100, 0100 and Zo=1, which means the question asks about the propagation delay for a very specific input.

Propagation delay usually depends on input values, so the answer will be lower than the maximum.

In this case, Z0=1, but X0=Y0=0, so the first adder outputs S0=1 and Z1 does not change, it stays at zero. So the inputs of the second adder (including its carry input) don't change at all, and it outputs S1=0, Z2=0.

Since the carry input for the third adder always stays at zero, adders 1 and 2 are not part of the longest propagation path... So we consider only the third and the fourth one.

enter image description here

So the answer would be XOR, AND, OR, AND, OR which is 70ns.

Note this is only valid if the top right AND gate involved in generating the first carry does not make a glitch on its output when one of its inputs switches from 0 to 1. If it does make a glitch, then that will propagate too, so the safe answer becomes the worst-case propagation time.

The usual AND gates don't glitch with one input switching, so in this case it's okay. But the XOR gate that sees its inputs going from 00 to 11 will glitch before it settles to 0 output, so it's part of the total delay.

  • \$\begingroup\$ Why is the FA3 xor and 2nd AND involved? That 2nd and only has one 1 and a 0, right? (Z3=0) shouldn't it be ((X3 and Y3) or 0) + FA4 (and + or) = 60ms? Oh, nevermind, now I get your last paragraph about glitching. Got it. \$\endgroup\$ Jan 1, 2022 at 22:51

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