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Why does the TTL NAND gate use 4 BJTs to make the gate when it could be done using only 2? I assume that the design with the 4 transistors amplifies the current so multiple levels of gates can be connected, while the one with 2 designs cannot power through several levels of gates?

enter image description here enter image description here

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    \$\begingroup\$ The second circuit is RTL. \$\endgroup\$
    – user16324
    Jan 1, 2022 at 18:07
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    \$\begingroup\$ Grand, the 2-BJT circuit is a circuit. But it isn't and cannot be made into a standard component. It's not used because it simply doesn't work well enough. It's a nice teaching tool. And that is where its usefulness mostly ends. \$\endgroup\$
    – jonk
    Jan 1, 2022 at 18:08
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    \$\begingroup\$ When chaining the 2-BJT gates, "output logic level" and so next "input logic level" will be degraded more and more ... problem of RTL logic. \$\endgroup\$
    – Antonio51
    Jan 1, 2022 at 18:24

3 Answers 3

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For the 2-transistor layout, R1 will always be a tradeoff between minimizing shootthrough current through Q1 and Q2 for a LO output (high R1 value) on the one hand and low output impedance on the other hand (low R1 value).

In the 4-transistor layout, either T3 or T4 will be on (push-pull layout), so the output pair wastes no current. As a result RC3 can be rather low and the output impedance will be much lower when sourcing current than for the 2-transistor design.

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  • \$\begingroup\$ Aside from the fact that the 2 transistor design isn't a design. It doesn't work and pretty much cannot be made to work. \$\endgroup\$
    – jonk
    Jan 1, 2022 at 18:07
  • \$\begingroup\$ @jonk I was writing without too much thought. What word instead of "design" do you recommend? "approach" perhaps? \$\endgroup\$
    – tobalt
    Jan 1, 2022 at 18:12
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    \$\begingroup\$ I was just commenting that the 2-BJT circuit is "mostly useless." There is no way to make it function as a standard building block. Can't be done. If anything, that was more the reason why it isn't and wasn't used. You treated it far too well in your writing. It almost sounded like a reasonable function block. (Which it is not.) That was my motivation for saying anything at all. But I think you wrote well for what was said. \$\endgroup\$
    – jonk
    Jan 1, 2022 at 18:15
  • \$\begingroup\$ I agree with these considerations about the circuit output... but couldn't they solve these problems by including a booster output stage in the second circuit as well? Note the two circuit solutions of logic gates are radically different in terms of their input. It would be interesting to see why... \$\endgroup\$ Jan 1, 2022 at 21:06
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    \$\begingroup\$ TTL design rules had never changed for input Vthreshold, and fanout of 10:1 . If any design does not meet this it isn't TTL. CMOS compatible TTL or 74HCT has the same input rule only, whereas std CMOs being symmetrical Rdson for Pch & Nch made the input threshold Vdd/2 , that is until very low Vdd designs became possible, then there is some offset due to Nch being only slightly lower RdsOn than Pch. By about 10% \$\endgroup\$ Jan 3, 2022 at 17:24
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TTL went thru about 6 types of circuit design including the classic combinations of std (54/74) , low-power (54/74L) and Schottky (54/74LS,S).

In every case the designs follow the same input rules for voltage threshold which is about 2 diode drops = 1.4V. Due to asymmetric impedance the margins for safe design were established from crosstalk as (0.8V to 2.0V. The average of these thresholds is 0.8+2.))/2= 1.4V . This 1.4 is the REAL switching threshold which only shifts due to 2 diode temperature effects. (est? < 8mV/'C)

The RTL design you show, is non-compliant.

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Since the output part has been considered so far, I will make some assumptions about the input part that implements the logic function AND (NAND).

Basic logic idea

As a rule, basic logic functions OR and AND are implemented by connecting electrically-controlled switches in parallel and series. These techniques are widely used in MOS and CMOS logic gates... and also, in the second OP's circuit where transistors are used as switches. But how is this implemented in the first OP's circuit?

Here, diode elements (T1's base-emitter junctions) are used as switches that, according to the rule, should be connected in series. But diode switches cannot be connected this way because they cannot be controlled. The problem of diodes is that they are 2-terminal (1-port) switches where the input and output occupy the same two terminals anode and cathode (base and emitter) while true controlled switches such as transistors are 2-port devices. So diodes can be connected only in parallel thus implementing OR function.

Implementation

To make them act as AND gate, they used a clever trick - inverting the inputs according to De Morgan's laws. That is why, they forward-biased the base-emitter junctions by the base resistor RB1 and connected them in parallel (through the outputs of the previous stage). Thus the OR circuit inputs (with respect to LOW input signals) were inverted and already implemented AND function (with respect to HIGH input signals).

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Fig. 1. Diode AND logic gate made from OR gate (taken from Wikimedia Commons)

I have explained this trick in the AND logic gate section of the Wikipedia page about diode logic.

Operation

Input logical "0" (at least one input). TTL gates exploit another clever trick both in the input and output part - if a single diode is connected in parallel to a string of diodes in series, the current is diverted (steered) to the single diode. See, for example, the movie from my personal Google Photos where my students connect a red LED (VF = 1.8 V) in parallel to a string of green and yellow diode (VF = 2.5 + 2.5 = 5 V); as a result, the red LED extinguishes the green and yellow one.

In TTL gates, the base-emitter junctions of the input multiple-emitter transistor T1 serve as "single diodes" and the network of its base-collector junction and T2 base-emitter junction in series serves as a "diode string".

So, when there is LOW applied to at least one input, its "diode" (with VF = 0.7 V) is connected in parallel to T1-T2 "diode string" (with VF = 0.7 + 0.7 = 1.4 V) and the whole T1 base current flows through the input "diode". As a result, there is no base current flowing through the T2 base-emitter junction and the latter is cut off.

Input logical "1" (at all inputs). In this case, all the "single diodes" are off. The whole T1 base current flows through the T2 base-emitter junction and T2 is on.

TTL advantages

If we compare the two solutions, we can see a significant advantage of TTL over the RTL input part. When at least one "0" is applied to an input, the multi-emitter transistor T1 is saturated and its collector-emitter part shorts the T2 base-emitter junction. As a result, T2 is reliably and quickly turned off.

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    \$\begingroup\$ You certainly can guess, but it's not even remotely true that you can only guess. There's plenty of written material on the topic, much of it by those very designers. \$\endgroup\$
    – hobbs
    Jan 1, 2022 at 23:29
  • \$\begingroup\$ @hobbs, If so, find it then and write an answer here... or show what I am wrong about. Because after all, I have done something by sharing my philosophy on the issue... \$\endgroup\$ Jan 2, 2022 at 7:55
  • \$\begingroup\$ Well, this answer could be improved by removing the sentence that says "we can only guess." \$\endgroup\$ Jan 2, 2022 at 15:20
  • \$\begingroup\$ @ Tanner Swett, Okay, I have removed the whole introductory sentence about circuit designers from the past. Let's give the opportunity to current designers here to tell us if this is the truth about TTL. I expect to see what their philosophy is. \$\endgroup\$ Jan 2, 2022 at 16:45

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