In short, I am trying to read data from a RAM's data bus via a FPGA. But the more lines from the bus I connect to the FPGA, the more distorted the signal become.
In more detailed, I have a FON2100 1 AP, running on 183 MHz, which has a HYNIX HY57V281620ETP-H SDRAM 2. I have attached the RAM's data bus to a Saprtan 6 (XC6SLX9) FPGA. I set the FPGA's pins to LVTTL (compatible with the RAM), and set them to FLOATING (hi-Z) mode. Currently there is a simple VHDL code on the FPGA that copies the input to an output when the WE is low (just for now).
When no line is connected to the FPGA, it's all good, device boots and works normally. However, the more line I connect to the FPGA, the more distorted the signal become until a point where the device doesn't work any more! It happens usually after connecting 6 lines. Here is an example of signal from two data lines: Before connecting
The same happens when I connect the lines to my logic analyzer  instead of the FPGA.
What is the issue, and what causes it? Any solution?