Connecting FPGA to a device's RAM data bus distorts signal - how to fix it?

Question

In short, I am trying to read data from a RAM's data bus via a FPGA. But the more lines from the bus I connect to the FPGA, the more distorted the signal become.

In more detailed, I have a FON2100 1 AP, running on 183 MHz, which has a HYNIX HY57V281620ETP-H SDRAM 2. I have attached the RAM's data bus to a Saprtan 6 (XC6SLX9) FPGA. I set the FPGA's pins to LVTTL (compatible with the RAM), and set them to FLOATING (hi-Z) mode. Currently there is a simple VHDL code on the FPGA that copies the input to an output when the WE is low (just for now).

When no line is connected to the FPGA, it's all good, device boots and works normally. However, the more line I connect to the FPGA, the more distorted the signal become until a point where the device doesn't work any more! It happens usually after connecting 6 lines. Here is an example of signal from two data lines: Before connecting

After connecting 5 lines

The same happens when I connect the lines to my logic analyzer [3] instead of the FPGA.

What is the issue, and what causes it? Any solution?

1 https://openwrt.org/toh/fon/fonera

2 https://www.alldatasheet.com/datasheet-pdf/pdf/113509/HYNIX/HY57V281620ETP-H.html

[3] https://www.dreamsourcelab.com/product/dslogic-series/

Answer 1

What is the issue, and what causes it?

Not perfectly clear, but: even although these SDRAM modules work at rather slow speeds, these RAM lines are still impedance-controlled transmission lines; just adding a piece of cable to them leads to a mismatch, and requires the line driver to drive a significantly higher load – no matter whether your FPGA is set to high-Z or a load impedance like 50Ω.

In fact, high-Z just means the power gets reflected at the inputs back into the transmission line, to meet with the original signal just where you connected your FPGA, thus degrading the signal by introducing both a higher load to the driver and adding echos!

You adding an oscilloscope with anything but a high-Ω probe (probe, not scope) only makes matters worse.

Any solution?

Yes, you must stop putting another transmission line in parallel to your RAM lines. Maybe you could design a flex PCB that has solderable connectors in the same pitch as your SDRAM IC, and carry an array of sufficiently fast buffer ICs? That way, you could keep the added line length short enough for it to not matter, and would have a high-Z sensing right at the place you need it. Also, add proper driver and sink termination to these buffers and your FPGA – "floating" input is almost never what you want with fast digital signals!

Answer 2

The timing on the SDRAM bus is rather tight and sensitive to transmission line effects. Adding extra wiring is adding stubs to the transmission line and upsetting the timing and voltage levels. Also, the SoC chip is most likely designed specifically to interface with only one memory chip and that is all.

I would suggest to keep the wires short (< 1") and some series resistance of around 33R might go some way to fix termination issues. How you physically achieve this is the challenge. You basically need to place the fpga on top of the ram chip! Maybe a flex pcb with the series resistors and buffer chips?

Due to the difficulties, I'd suggest you rethink what you want to do. Yes, wifi routers are dirt cheap, but the chips are designed for a specific function and that is all. You might have better luck interfacing via the quad spi or choosing a wifi router that has pci express. Or a sbc like RasPi, Beaglebone or ZYNQ?

Answer 3

Thank you all for helping.

I added series termination resistors, and it solved the issue. Here is a sample of signal after adding termination resistor:

As already mentioned, I'd need to design a flex PCB, but I think having these resistors and connecting them on a breadboard is a cheap and fast solution for now :)