I'm following a discussion board that discusses an ASIC chip they are building, and they are using terms that I'm unfamilliar with. So far I've gathered
- Once a logic design is tested on an FPGA it can be ported to an ASIC with relative ease.
- The ASIC is created on a Wafer of ~1000 chips
- That wafer is chopped up into smaller chips called "dicing"
- Packaging: (not sure what this means: "Aligning the substrates to the fiduciary marks")
As you can infer, I'm a little confused and overwhelmed by the process, but I want to get a handle on what is required and what the end to end process looks like.
Where can I find a detailed list of what happens after I test my FPGA logic and am ready to create several thousand ASICs based on that design?