# Absolute Maximum logic voltage best practices

I'm interfacing a PIC24FJ MCU along with a Microchip BM83 BT module. The absolute maximum ratings for the "logic high" level show 3.6 V (with 3.3 V as nominal) on any given I/O port of the BM83. Similarly, the PIC expects, on any pins that are not 5V tolerant, a 3.3 V nominal level for high and 3.6 V absolute maximum.

My question is: would best practice here be to use the 5 V tolerant pins, since I don't want to possibly drive the standard pins to their absolute maximum, or do manufacturers expect that a given I/O pin will not stay at its maximum possible voltage for prolonged periods of time?

Here are the relevant excerpts from the datasheets:

BM83

PIC24FJ

• You haven't explained why these pins may receive voltages higher than 3.6 volts. This is a fundamental part of the question that needs explaining and, you need to explain where these "rogue" voltages come from and how high they might be. In other words; describe the threat. You also need to link the data sheets for the two devices. Commented Jan 4, 2022 at 16:39
• @Andyaka The 3.3v LDO I'm using is rated to output 3.6V at the absolute maximum. The BM83 uses its own LDO, but I suspect it has similar ratings. It's not so much that I know that a thread exists, rather that I'm trying not to fall into a trap for newbies. :) Commented Jan 4, 2022 at 16:47
• I'm not understanding where there is a problem then. Commented Jan 4, 2022 at 17:00

If your design your external drivers to use the same 3.3V supply and have long traces or wires, you can reduce overshoot by adding 100R to the signal then the tiny ESD protection diodes rated for only a few mA limited by 10k resistors in two stages won't have to do any protection. But if the chip after ESD diodes gets > 1 Sh. diode drop above rail, then chip crowbars the supply. But the 2 stage ESD diode clamps work Ok on both over and undershoot in most cases. (SCR mode substrate well known failure)

So if you inadvertantly use 5V logic with 25 to 50 Ohm typical impedance drivers, then you need 5V protection.

When the signal prop. Delay approaches the rise time of the ns pulses overshoot and ringing occurs naturally due to transmision line impedance mismatch effects. That's why adding a series R dampens this to closer match the wire or long trace impedance. Use v=2/3c for most dielectrics to compute prop[delay] annd datasheet with pF load to estimate rise time.

EDIT After reading the datasheet , the Vbat limit is 4.2V which normally powers the unit. Snip from datasheet.

5.1 Power Supply The BM83 module is powered through the BAT_IN input pin. The following figure illustrates the connection from the BAT_IN pin to various other voltage supply pins of the IS2083BM SoC on the BM83 module. The external 5V power adapter can be connected to ADAP_IN in order to charge the battery in battery powered applications or in USB applications. Otherwise the ADAP_IN pin can be left floating if there is no battery utilized at BAT_IN pin.

• The BM83 suggests applying 5V to it and letting its internal vreg drop that to VDD_IO (3.3V). It's technically possible for me to use the same 3.3V rail if I apply 3.3v at the "Battery Input" pin of the BM83. Would I still be okay using the 100R inline resistors if I use the 5V input (as is suggested by the D/S)? Commented Jan 4, 2022 at 16:34
• Your last edit with the copy and paste from the D/S -- is the implication here, from the last sentence, that I read it wrong all along and as long as I'm not using a battery (I'm not), I should to power the module using BAT_IN and the standard 3.3v rail? The unit is powered using a 12V input, with a 12V->5V buck then a 5v->3.3v LDO, for what it is worth. Commented Jan 4, 2022 at 16:55
• If not charging a battery then use 3.3 for BAT_IN and leave out ADAP_IN Commented Jan 4, 2022 at 17:51