It’s not about the low voltage per se, it’s about the signal integrity. Any kind of transition introduces a possible impedance discontinuity which distorts signals and reduces margins.
This loss or margin is sometimes referred to as 'closing the eye', meaning that there isn't enough margin left to allow for reliable clocking of the signal given all the other variations in timing arising from other causes, like push-out, clock jitter and signal-to-signal coupling.
Modules have several issues that work against signal integrity (eye opening):
- Connector discontinuity (signal distortion)
- Reference plane discontinuity (signal distortion)
- Routing skew / longer traces (delay uncertainty)
- Power stability (push-out / delay uncertainty)
Longer traces also add to latency. This can be compensated for in the controller, but nonetheless impacts performance (read latency especially.)
Given LPDDR4x small I/O swing and very high per-bit throughput, it may very well be that LPDDR4x lacks tolerance to allow for signal distortion inserted by connectors and reference plane changes, at least if it is to run at its full clock rate.
The SI impact something that a designer would need to model as a system when designing the module and the motherboard.
This all said, there's been moves on the data center side of things to address the limitations of DDRx. One is High Bandwidth Memory (HBM), which uses stacked die placed nearby the processor. A competing technology, Hybrid Memory Cube (HMC) is similar in that it also uses stacked die, but adopts a serdes interface and thus is somewhat more tolerant of layout and possible modularization.
More about HBM and HMC here: https://www.eetimes.com/hbm-flourishes-but-hmc-lives/