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I am trying to calculate the overall efficiency of a PFC+flyback converter. The PFC boost converter has an efficiency of 0.9 and the flyback an efficiency of 0.89. Depending on the load which requires 374 W (from flyback), I designed the PFC stage to provide 416 W. Since the PFC has a 0.9 efficiency, the input power is 462 W. This brings down the overall efficiency to 374/462 = 0.81. Am I wrong in this calculation? Or does the PFC stage adjust its power input and output depending on the load power requirements?

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  • \$\begingroup\$ 374 W from a flyback sounds like a poor design choice. \$\endgroup\$
    – winny
    Jan 6 at 12:36
  • \$\begingroup\$ And 0.89 efficiency sounds unrealistic. At that power level, think 0.69. Where did your efficiency numbers come from? Have you included core losses? \$\endgroup\$
    – AnalogKid
    Jan 6 at 13:20
  • \$\begingroup\$ @winny guess I'll have to do more research on this. What is the best topology for such a power level \$\endgroup\$
    – p_karis
    Jan 6 at 13:27
  • \$\begingroup\$ @AnalogKid what should I consider in designing at such a power level? targeting a +90% efficiency? \$\endgroup\$
    – p_karis
    Jan 6 at 13:29
  • \$\begingroup\$ Since you don't give any idea of your input or output voltage requirements it's difficult to suggest alternative topologies. \$\endgroup\$ Jan 6 at 13:42

1 Answer 1

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This brings down the overall efficiency to 374/462 = 0.81. Am I wrong in this calculation?

Nope. It's maths.

Basically, you have two cascade-connected converters (i.e. PFC's output is the main regulator's input). This means that the output power provided by the PFC pre-regulator is taken by the main regulator, and some portion of this power will be delivered to the load. So, mathematically, the overall efficiency is the multiplication of each cascade-connected converters:

$$ \eta=\frac{P_{out}}{P_{in}}=\frac{P_{out}}{P_{in-flyback}}\cdot\frac{P_{out-PFC}}{P_{in-PFC}}=0.9\cdot0.9=0.81 $$

\$P_{in-flyback}=P_{out-PFC}\$ because the output power of the PFC is the input power of the main regulator.

or does the pfc stage adjust its power input and output depending on the load power requirements?

Not quite. PFC regulator makes some adjustments for betterment of the power delivery. Though it can limit the power delivery or stop the delivery if the delivery exceeds a certain level (i.e. overload protection). But these do not mean that PFC pre-regulator adjusts its power input.

The controller block and some other surrounding sub-circuits always consume some power (Though today's controllers are intelligent enough to decrease the power consumption at different situations). The input power is the sum of the output power and the consumption of the internal circuitry:

$$ \eta=\frac{P_o}{P_i}=\frac{P_o}{P_o+P_d} $$

The consumption of the internal circuitry, \$P_d\$, can increase or decrease depending on the output power but let's assume it constant for a moment. As you can see from the equation above, the greater the output power the greater the efficiency:

$$ P_d=1; \ \ \ \mathrm{assume \ constant} \\ \eta=\frac{P_o}{P_o+P_d}=\frac{2}{2+1}>\frac{5}{5+1}>\frac{50}{50+1} $$

So we can say that the maximum efficiency can be obtained at maximum power output. We assumed \$P_d\$ to be constant but, for example, at 50W output it may go up to 4W but the overall point still holds.

PS:

the load which requires 374W(from flyback)

Flyback would be the worst topology for that level of power. I'd kill myself if I didn't tell this. Don't ask for topology recommendations under the comments section because it's a different topic.

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  • \$\begingroup\$ thanks a lot. I'll have to do more research on power topologies. But lets say I used an appropriate topology, how can I maximize the efficiency to +90% from a boost PFC stage? \$\endgroup\$
    – p_karis
    Jan 6 at 13:23
  • \$\begingroup\$ A properly designed boost PFC stage will normally give greater than 90% even at relatively low (e.g. less than 100W) output power levels (One of my designs which is a 60W BCM boost PFC gives 93% at half load, and 95% at full load). The design should be carefully done, and the components (MOSFET, diode, inductor etc) and the operation mode of the topology (i.e. DCM, CCM or CrCM) should be properly selected/designed. \$\endgroup\$ Jan 6 at 13:41
  • \$\begingroup\$ Thanks again. I appreciate \$\endgroup\$
    – p_karis
    Jan 6 at 13:51

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