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In IEC 60664-1:2021 table F.5 (former F.4): Creepage distances to avoid failure due to tracking or 60950-1:2005 Table 2N – Minimum creepage distances the second and third columns are applicable for "printed boards" or "printed wiring materials". For voltages below 1000V and a pollution degree of 2 or 1 the creepage distances are far shorter then the "general" distances (see Creepage distance for PCBs handling line voltage AC? for the table extracts of IEC 60664-1).

  • What is the reason to allow shorter creepage distances for PCBs than for other materials?
  • Are there any restrictions to allow the application of the shorter creepage distances?
  • Are the shorter distances only applicable for bare PCBs or also for assembled ones?

I was not able to find a satisfying answer to my questions in the standard or in the application guide IEC 60664-2-1 or in the internet. The only phrase that may give a hint was the following (but I find it rather ambiguous):

For creepage distances on printed wiring material only used under pollution degree 1 and 2, a reduced dimensioning is applicable according to IEC 60664-1. Attention is drawn on the possible reduction or other path of creepage distances due to the components.

But the main question for me is my first one: Why for PCBs it is allowed to use shorter creepage distances? I really can't see a reason.

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3 Answers 3

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What is the reason to allow shorter creepage distances for PCBs than for other materials?

The difference is the electrical breakdown of the material and resistivity of the material and the chance of arcing. PCB's also have soldermask that can help reduce the chance of arcing.

Are there any restrictions to allow the application of the shorter creepage distances?

It depends, mostly on two things.

  1. If the design is going to have to pass IEC requirements (like IEC 61010) at a National Recognized Testing Lab (NRTL), if so, then the design will need to follow the creepage\clearance distances in the table. If the design does not conform to the
  2. If the design should prevent arcing -- The design doesn't have to follow IEC requirements, but the chance of arcing increases if the minimum crepage\clearance for the appropriate voltage is not followed. A design should follow these requirements.

There is one thing that can be done to make the design more compact, but also follow the creepage\clearance distances, and that is to introduce insulative barriers or slots in the PCB, as shown below:

enter image description here
Source: https://forum.mysensors.org/topic/4175/clearance-creepage-and-other-safety-aspects-in-mysensors-pcbs

Are the shorter distances only applicable for bare PCBs or also for assembled ones?

The design should conform to air clearance distances between any two conductors. So if the PCB meets the requirements, but after assembly there are components that decrease the clearance values between two different conductors with different potentials, then it will not meet IEC requirements. For example, if the air clearance requirement between conductors was (say) 2mm and after assembly a connector reduced that to 1mm it would not meet the IEC spec and the design would not pass at an NRTL.

But the main question for me is my first one: Why for PCBs it is allowed to use shorter creepage distances? I really can't see a reason.

The difference in the table is internal vs external signals and if they come into contact with air or not. An internal signal has PCB material between it and other conductors. If you notice in the table if external conductors are coated (B4) then they have clearances that are close to internal PCB traces (but not the same).

This is my opinion: Air can have varying properties (humidity changes the conductivity) and if a conductor is exposed to air, it is probably also exposed to dust and other materials so the IEC requirements reflect that and increase the distance which reduces chances of arcing.

enter image description here
Source: https://electronics.stackexchange.com/tags/creepage/info

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  • \$\begingroup\$ Thank @Voltage Spike your for answering my question. But for me it is still not clear. Maybe I should go with examples. Let's say there are 100V DC between primary and secondary circuit. If you have a look in ISO 60664-1 Table F.5 DP2 Material IIIa you have for "printed wiring material" a distance of 0.160mm but for non printed wiring material 1.4mm. \$\endgroup\$
    – Hellfish
    Jan 11, 2022 at 20:40
  • \$\begingroup\$ - Can I apply the 0.160mm for every kind of PCB? - Can I apply the 0.160mm for two solder pads or only for two lanes? - Can I apply the 0.160mm for the IC the is soldered to the pads? Or do I need to apply the 1.4mm in that case (depending on the Material category of the IC)? \$\endgroup\$
    – Hellfish
    Jan 11, 2022 at 20:40
  • \$\begingroup\$ If I understood you correctly you are stating, that it is well established the PCBs have shorter creepage distances. But unfortunately the standards don't reveal any explanation why.... It's just that I have found nowhere in the standard or in ISO 60950-1 some conditions to be allowed to apply 0.160mm instead of 1.4mm. There is nothing about coating, soldermask or anything. In ISO 60950-1 it is stated that you may use the table 2N (which contains the same distances) for uncoated boards. \$\endgroup\$
    – Hellfish
    Jan 11, 2022 at 20:40
  • \$\begingroup\$ I stated a reason of 'why' in the answer. The real reason would lie in countless testing and safety documents that are only internal to the IEC. I am not a regulatory consultant so I can only give you the experience that I have had with regulatory\NRTL's. I rely on consultants heavily when it comes to interpreting requirements. "Can I apply the 0.160mm for every kind of PCB? -" Probably not, the PCB needs be made from materials that conform to IEC/IPC standards. \$\endgroup\$
    – Voltage Spike
    Jan 11, 2022 at 23:09
  • \$\begingroup\$ Can I apply the 0.160mm for two solder pads or only for two lanes? - Any two conductors that has the voltage separation needs appropriate spacing. So if the two lanes are both at 100V differential voltage, then they need 100V spacing. If they are both 100V, then they need very little spacing. If you have a part that does not have adequate spacing then it will not pass NRTL certification. Additionally most of the parts that do touch AC mains will also need to have UL/IEC certifications if they are on the critical components list. \$\endgroup\$
    – Voltage Spike
    Jan 11, 2022 at 23:10
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Note C in table F.2, states: For printed wiring material, the values for pollution degree 1 apply except that the value shall not be less than 0,04 mm, as specified in Table F.5. A protection by means of a solder resist of high quality is the minimum requirement to allow this clearance reduction.

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I believe this column only applies to Coated boards. It is clearer in the new IEC62368 standard which replaced IEC60950.

I do sympathise with the original poster. I also found this part of the IEC60950 standard very confusing. I'm now confident that the numbers in Table 2N "Printed Boards" were intended to apply only to boards that are coated. IEC60950 Section 2.10.6 makes the distinction, and the numbers in IEC60950 Table 2N (Printed Boards) correspond to the numbers in the newer standard IEC62368 Appendix G Table G13. Appendix G in IEC62368 states that for Uncoated Printed Boards, the same creepage and clearance requirements apply as for other situations. For Coated Printed Boards it refers to Table G13 where the numbers match the "Printed Boards" column in IEC60950 Table 2N (Still a little confusing - 62368 table G13 is peak voltage, 60950 Table 2N is RMS so the 50V line on Table 2N corresponds to the 71V line on G13).

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