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I have written tb in verilog. My testbench inputs are going at high impedance i.e. zz. My dut is not able to force stimulus.Please help me as I m not able detect the problem in my testbench.

module_tb()

 reg [47:0]  data_out_1;  
top_design uut1(
           //inputs

            .clock(clk),
           .reset(rst),
           .data_in(data_i),
           .dcsel(dcsel),
           .xlat(xlat),
           .blank(),
           .RD(read),
           ///OUTPUTS
           .Data_out(data_out_tb));
 initial 
       begin
      //inialize 
inputs

      #1 rst=0
      exp_case_2a(data_out_1);
      exp_case_2b(data_out_1);
      #100000 $finish;
       end
 task   operation_1;

      reg [47:0] data_out_1;
      begin
     exp_case_2a(data_out_1);
      end
   endtask 

   task   operation_2;

      reg  [47:0]  data_out_1;
      begin
     exp_case_2b(data_out_1);
      end
   endtask 

 task exp_case_2a;

      reg data_i;
      reg reset;
      reg read;
      reg dcsel;
      reg xlat;
      output [47:0] data_o;
      begin
         repeat(47)begin@(posedge clk)
       data_i = 1;
        reset = 0;
        read = 0;
        dcsel = 0;
        xlat = 0;
        data_o = Data_out;
         end    
     @(posedge clk)
       begin
          data_i = 0;
          reset = 0;
          dcsel = 0;
          xlat = 1;
          read = 1;
          data_o = Data_out;
       end

         #5250  compare_data_2(data_out_tb); 
      end   
   endtask // exp_case_2a


   task exp_case_2b;

      reg  data_i;
      reg  reset;
      reg  read;
      reg  dcsel;
      reg  xlat;
      output [47:0] data_o;
      begin
     repeat(47)begin @(posedge clk)
       data_i = 1;
        reset   = 0;
        read = 0;
        dcsel = 0;
        xlat = 0;
        data_o = Data_out;          
     end
     @(posedge clk)
       begin
          data_i = 0;
          reset = 0;
          read = 0;
          dcsel = 0;
          xlat = 1;
          data_o = Data_out;
       end   
     #5250   compare_data_2(data_out_tb);
      end       
   endtask 

 /* ...........  SCORE-BOARD..............  

   task compare_data_1;               
      input [47:0] exp_data;

      begin        
     if(exp_data == `comp_data_1 )
       begin
          $display("test passed 0");
          -> error; 
       end
     else
       begin
          $display("test failed 0");  
          -> error; 
          err_cnt_1 = err_cnt_1 + 1;
       end // else:
      end
   endtask
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Although there are other issues, your basic problem is that the (implicit) wires that you have connected to your unit under test are not driven by anything.

The reg variables with the same names that you have declared within each task are local to that task, and have nothing to do with the top-level wires.

If you want the task to be able to read and/or drive wires in the top level, you need to pass those connections as arguments to the task, and declare them as inputs and/or outputs within the task itself.

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  • \$\begingroup\$ Thanks for your reply .I tried out passing for eg exp_case_2a(data_i_g,rst_g,read_g,dcsel_g,xlat_g,data_out_1); inside "task operation_1 " and declare it as input /output .But still its not working. \$\endgroup\$
    – Manzer
    Mar 10 '13 at 13:09
  • \$\begingroup\$ I think I would suggest at this point that you write a simple version of your testbench without tasks, get it working the way you want, and then organize it into tasks so that it can be extended. \$\endgroup\$
    – Dave Tweed
    Mar 10 '13 at 13:29

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