For a size reference, the tracks are 0.254mm wide and the distance between them is also 0.254mm. It passes all DRC's but I'm just wondering if I will have capacitance or inductance problems between the traces. Hope someone can help, thanks.
Probably not, there is most likely not more than 10pFs of capacitance between those traces, and probably not much mutual inductance (nH's of inductance and probably not a great coupling value), so any parasitic values will probably be less than mV's of noise on the other trace. It depends on how long the traces run parallel though. Since it's digital, the logic levels matter. If you are running 1.8V CMOS digital levels you might have to worry about it. But I'm willing to bet the design runs 5V or 3.3V TTL or CMOS, the transitions of those standards are at 1.5V, and it would take a lot to get that kind of voltage to mistake a transition.
If you are worried about it, estimate/calculate the capacitance and inductance between the traces with a PCB trace calculator and then either simulate it or draw it on the schematic and ask yourself if it would be an issue (like draw a 10pf cap (or whatever your estimate is) between the nets on the schematic)
Its fine, but as others have said:
control edge slew rates, e.g. by using small resistors in line with digital outputs. This is only needed if you have some very fast logic around (e.g. LVC)
your bigger problem is the lazy pour. Throw down lots of stitching vias, so that the pour has no dead ends.