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I'm working on a digital circuit that I plan to run at ~1MHz. After finishing the PCB I looked back at my work and saw that my tracks are quite close. My PCB

For a size reference, the tracks are 0.254mm wide and the distance between them is also 0.254mm. It passes all DRC's but I'm just wondering if I will have capacitance or inductance problems between the traces. Hope someone can help, thanks.

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    \$\begingroup\$ Not enough information. If track width and space alone was a criteria, then you’d have trouble with smt ics as they have pins very close to each other. Distance, edge rate, frequency, logic type and levels etc. Looking at your top fill, I’d be more concerned with that as it looks like there’s plenty of antennas. \$\endgroup\$
    – Kartman
    Jan 7 at 6:12
  • \$\begingroup\$ Any tips on how a can make my top-fill better? It shouldn't matter too much because it is all grounded right? \$\endgroup\$
    – Matthew
    Jan 7 at 6:28
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    \$\begingroup\$ Looks like your vcc needs fattening up. One ic has round pads, the other rounded rectangles. The rounded rectangles are easier to solder. \$\endgroup\$
    – Kartman
    Jan 7 at 6:28
  • \$\begingroup\$ Why use a top fill? You’ve got a gnd plane on the bottom - concentrate on getting that as good as possible - as in as few breaks as possible. \$\endgroup\$
    – Kartman
    Jan 7 at 6:30
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    \$\begingroup\$ @MituRaj The problem may not be the frequency of the signals, but rise/fall time of the edges, as too fast edges can ruin even a 1 Hz signal integrity. And there's too little information to make a conclusion. \$\endgroup\$
    – Justme
    Jan 7 at 6:41

2 Answers 2

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Probably not, there is most likely not more than 10pFs of capacitance between those traces, and probably not much mutual inductance (nH's of inductance and probably not a great coupling value), so any parasitic values will probably be less than mV's of noise on the other trace. It depends on how long the traces run parallel though. Since it's digital, the logic levels matter. If you are running 1.8V CMOS digital levels you might have to worry about it. But I'm willing to bet the design runs 5V or 3.3V TTL or CMOS, the transitions of those standards are at 1.5V, and it would take a lot to get that kind of voltage to mistake a transition.

If you are worried about it, estimate/calculate the capacitance and inductance between the traces with a PCB trace calculator and then either simulate it or draw it on the schematic and ask yourself if it would be an issue (like draw a 10pf cap (or whatever your estimate is) between the nets on the schematic)

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Its fine, but as others have said:

  1. control edge slew rates, e.g. by using small resistors in line with digital outputs. This is only needed if you have some very fast logic around (e.g. LVC)

  2. your bigger problem is the lazy pour. Throw down lots of stitching vias, so that the pour has no dead ends.

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  • \$\begingroup\$ I'm not clear about where you mean to put the stitching vias. When you say to put it around the dead ends, do you mean to put them around the edges of places such as the trapezium under the pins U11_8, U13_4, U12_6? \$\endgroup\$
    – Matthew
    Jan 11 at 7:52
  • \$\begingroup\$ @Matthew yes exactly. Stitching means to make the two patchy GND "planes" (obtained by bottom and top pours) work as one single contiguous plane by "bolting" it together at many places allowing return currents to flow without large detours. Especially, avoid dead ends that are long and narrow like above U13_1 (those are all small antennas) or terminate them with a via. \$\endgroup\$
    – tobalt
    Jan 11 at 8:41
  • \$\begingroup\$ is there a way I can just cut off some parts of the pour? For example, the one that you mentioned, the one above U13_1, since there is a track below where I should put the via, can I just cut off that part of the pour? \$\endgroup\$
    – Matthew
    Jan 11 at 8:48
  • \$\begingroup\$ @Matthew If it is inconvenient to put a via because you can't fit it in, then it is indeed better to avoid those parts of the pour altogether in my opinion. As these are dead ends, the anyway cannot be part of a return current loop and their only function is parasitic (antenna). \$\endgroup\$
    – tobalt
    Jan 11 at 10:42
  • \$\begingroup\$ Yeah ok, is it the geometry of that part of the pour that makes you say that I should get rid of it, or is it just the fact that it doesn't need to be there since it does not lead to any GND pin? I ask this because if you have a sharp geometry and then have a voltage spike(induced by ground bounce in this case), then it is more likely to induce a voltage into nearby tracks, right? \$\endgroup\$
    – Matthew
    Jan 11 at 10:54

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