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The phase noise plot for a particular crystal oscillator is here. The datasheet represents an entire series of oscillators which range in frequency from 1 to 75MHz. The phase noise plot is indicated as "typical" but shows that it was measured for a carrier frequency of 50MHz.

If a 5MHz frequency oscillator were selected from the series instead of 50MHz, would one expect it to have the same phase noise or proportionately lower phase noise? In other words, would it have higher RMS jitter or equivalent?

If the end goal is produce a 5MHz clock signal with minimal RMS jitter, is it generally advantageous to select the 50MHz model and divide* it by 10 or simply select the 5MHz model?

*I understand RMS jitter does not improve with clock division, but if the higher frequency oscillator has superior RMS jitter compared to the lower model, then this may be a winning strategy.

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  • \$\begingroup\$ If the DS doesn't give you confidence, speak to the supplier. If the supplier doesn't give you confidence then choose a different supplier. That's how we (as engineers) can make the world a tiny bit better. \$\endgroup\$
    – Andy aka
    Commented Jan 7, 2022 at 8:01

3 Answers 3

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'minimal RMS jitter' is not a specification. How much do you want to spend? Fundamental oscillator? Overtone oscillator followed by an injection locked divider? Rubidium? Hydrogen maser?

Select the 5 MHz model and evaluate it. If it doesn't give you the performance you want, then characterise where it's deficient and improve it. Simply going for a different solution, say 50 MHz and dividing by 10, is as likely to make things worse as better, depending on what is important in your application. The divided solution will be better close to carrier (100-1k), and have worse far out noise floor (100k and out). Which of those is more important for your application?

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    \$\begingroup\$ "The divided solution will be better close to carrier (100-1k)" Could you slightly expand on this please? Wouldn't that mean that the high-frequency source clock before division had a lower close-in noise than the comparable low-frequency clock in the first place? This would be probably meaningful information for the core question of the OP, but also for me 😉 \$\endgroup\$
    – tobalt
    Commented Jan 7, 2022 at 9:05
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    \$\begingroup\$ It depends what method of division we are talking about for close in noise. If with digital logic, then phase noise is improve (by increasing the period) but absolute jitter remains the same or gets worse, due to the logic adding its own jitter . If using a subharmonic injection locked oscillator, or a DDS, then both can be improved due to the averaging of many edges, or degraded if the additional noise is greater. It's non-trivial to specify and work with very low phase noise devices. Hence evaluate the 5 MHz device first. \$\endgroup\$
    – Neil_UK
    Commented Jan 7, 2022 at 9:30
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For quartz crystal oscillators the biggest contribution to the jitter comes from random noise sources. So there should not be a direct relation between the RMS timing jitter and the oscillation frequency. NOTE: since the RMS jitter is in the orders of picoseconds or even less than 1 picoseconds, it's neglected (i.e. not considered as a limiting parameter or reason for preference) for less than 10 (or even 50) MHz in most applications.

However, for crystal-based active clock sources, the jitter might be a bit higher and a bit more predictable, depending on the design, because the RMS jitter varies with the supply voltage as well.

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    \$\begingroup\$ Your "NOTE" is certainly not universally valid. E.g. for high precision data converters, you often use clocks in the range of 10-30 MHz. And jitter absolutely matters already for signals in the 10s of kHz range. Better than 1 ps RMS is beneficial in many applications of such "low" frequency clocks. \$\endgroup\$
    – tobalt
    Commented Jan 7, 2022 at 7:30
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    \$\begingroup\$ @tobalt you're right, I should've put "in most applications". Thanks. Fixing... \$\endgroup\$
    – Rohat Kılıç
    Commented Jan 7, 2022 at 7:33
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If the end goal is produce a 5MHz clock signal with minimal RMS jitter, is it generally advantageous to select the 50MHz model and divide* it by 10 or simply select the 5MHz model?

Assuming high frequency oscillators had lower RMS jitter (which I will leave to other answers to confirm/disprove), you will have to divide the output frequency as you correctly assess.

If you do that with some off-the-shelf Flip Flops, those will add much more jitter than good oscillators.

If you divide with a PLL, then the source jitter will be filtered out anyway.

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