How do we justify small signal analysis of comparator while we know that the biasing condition for the input devices are different?

During the real operation of comparator, the input baseline is lower than the threshold voltage. How do we justify small signal analysis of comparator while we know that the biasing condition for the input devices are different? am I forgetting some basic theoretical understanding here?

• Why would you want to justify it? Jan 8 at 21:29
• @Andyaka because, as I understand it, small signal is valid only around the biasing point. In the comparator case, the input devices are biased at different point. Jan 8 at 21:34
• Small signal analysis is only valid when the circuit behaves linearly. A comparator does that only when the input voltage (difference) is near zero. I would generally not care about that behavior as it is not a state in which the comparator spends much of its time. A comparator spends most of its time in its non-linear state. Also the time response behavior (speed) of a comparator is mainly determined by slew-rate which is a large signal behavior. Jan 8 at 21:45
• It's true that large signal slew rate is a factor, but decision (switching) and settling time is a function of resistance and capacitance. The resistance is defined by the small signal gm (inverse). So fast transitions are dependent on this value. Mismatch is function of area (large L*W => better matching). So large gm faster, but that also requires low L. There's tradeoffs here. These design choices are governed around the small signal analysis and center of the decision threshold point. Your thoughts seem ok on that.
– pat
Jan 8 at 22:06
• 2nd pole is usually best pushed out far from 1st You want to avoid too much ringing and problems associated with non-dominant poles occurring before gbw. I would simulate step response and optimize around speed and settling characteristics. Slew Rate is an issue, but the assumption is you have enough not to affect linear settling characteristics.
– pat
Jan 8 at 22:20