Problem in implementing D Flip Flop with asynchronous Reset using Verilog

Question

I was implementing the D flip flop with asynchronous reset in Verilog. This is the code that I put in:

module d_ff_A (input Clock, input D, input Rst, output Q);
wire Clock, D, Rst;
reg Q;
always @(negedge (Rst) or posedge (Clock))
begin
if (!Rst)
Q=0;
else 
Q=D;
end
endmodule

Now while creating a test bench, I used the following code:

`timescale 1ns/1ps
module stimulus;
    reg Clock;
    reg D;
    reg Rst;
    wire Q;
    d_ff_A uut (.Clock(Clock), .D(D),.Rst(Rst), .Q(Q));
    
    integer i;

initial begin
    $dumpfile("test.vcd");
    $dumpvars(0,stimulus);
    D=0;
    Rst=1;
    #8 D=1;
    #10 D=0;
    #10 D=1;//Rst=1;
    #10 D=1;
    #10 D=1;//Rst=0;
    #10 D=0;
    #10 D=1;
    #10 D=0;
    #6  D=1;
end

initial begin
    Clock=0;
    for (i=0; i<=10;i++)
        #10 Clock=~Clock;
end
initial begin
    #40 Rst =0; //have created a negative trigger
end
endmodule

Now the problem I am facing is, even though, say at t=50, reset = 0, D=1, Clock=positive triggered and my reset is neg triggered while executing the always @(negedge (Rst) or posedge (Clock)) , when it runs for the positive triggered clock, it sees that !Rst=1 and resets the output.

The workaround for this would be to set Reset =1 afterwards and run the code. I was wondering if there's a better way?

Answer 1

What you are doing in the testbench is legal; however, it is more common to assert the reset signal starting at time=0. Since your reset is active-low (due to the negedge (Rst) in your design), that means you would set Rst=0 at time=0, then set Rst=1 at time=40 in the testbench. In general, it is a common practice to first reset your logic, then release the reset.

Here is the modified code (with some indentation):

initial begin
    $dumpfile("test.vcd");
    $dumpvars(0,stimulus);
    D=0;
    Rst=0;
    #8 D=1;
    #10 D=0;
    #10 D=1;
    #10 D=1;
    #10 D=1;
    #10 D=0;
    #10 D=1;
    #10 D=0;
    #6  D=1;
end

initial begin
    Clock=0;
    for (i=0; i<=10;i++)
        #10 Clock=~Clock;
end

initial begin
    #40 Rst = 1;
end

It is also conventional to denote active-low signals in the signal name by using an n prefix or suffix. For example: nRst or Rst_n. Other common prefixes are _b and _bar.