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I have been trying to design a first-order circuit with a capacitor but, I could't achieve to initaliaze the steady-state condition. I mean I was not able to close the switch at t = 0. Since, I am using a dc voltage source, at t = 0 capacitor voltage must be equal steady-state value. My question is how can I achieve that?This the circuit which I am trying to obey.

Could you tell me which block should I use ın Simulink?

This is the circuit that ı had designed This is the circuit that ı had designed.

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The problem with these questions is t=0 does not imply that at t=0 the power is also applied, they imply t=-∞ the power supplies are "turned on" and a steady-state condition is achieved.

This is crucial when you consider how simulations work since they typically by default initialize with current and voltage all at zero and thus if a switch is commanded at t=0 the result mentioned in the question will occur, no matter the simulation engine used.

Different simulation packages solve this in different way and one of them is performing a DC bias point "pre simulation". Simulink is no different but how you solve this is up to you and upto "convinience"

Without doing anything this is the results enter image description here

OPTION #1 redefine t=0 to be t=TBD where TBD is determined via separate simulation, ~ 3.3seconds.

enter image description here In this instance you can see at t=5 the step is enabled

OPTION #2 If you determine the DC bias point (separate simulation), you can set the initial voltage on the capacitors and have a step time of t=0

enter image description here

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  • \$\begingroup\$ I am so appriciated for your answer. But can I ask you which value you have assigned for the series resistor parameter in the capacitor ? \$\endgroup\$
    – Sannet
    Jan 10, 2022 at 12:56

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