Iam trying to simulate the loading behavior of an EEPROM. It is powered by a 5V LDO. When would the EEPROM actually consume power?

  1. Does it consume power during the entire read/write cycle time? As per my basic understanding, digital ICs only consume power during state transitions. If so, shouldn't we be considering the sum of all rise/fall time for power calculation within a write cycle.

enter image description here

  1. Why does this source refer to both rise time energy and write energy? enter image description here Disclaimer: Iam not a digital guy and know very little about the timing parameters.
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    \$\begingroup\$ Everything consumes power when statically operated. It may not be much, but, it's always present. \$\endgroup\$
    – Andy aka
    Commented Jan 10, 2022 at 18:00
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    \$\begingroup\$ Think about it... why does a write cycle take so long? \$\endgroup\$ Commented Jan 10, 2022 at 19:25
  • \$\begingroup\$ @BruceAbbott: It takes multiple clock cycles to complete a write operation (which might consists of many sub operations). Thats all I can infer from that \$\endgroup\$ Commented Jan 11, 2022 at 7:09

3 Answers 3


Here is an example write current waveform from the NXH5104 4 Mbit Serial SPI EEPROM datasheet.

enter image description here

In the table of 'Static characteristics' the average write supply current with 4 sectors active and 5 MHz SPI is specified as 1.1 mA at 1.2 V. In the trace we do see a continuous current draw of ~1.1 mA. However there are also large 4 large spikes not directly related to SPI bus activity. The total charge consumed during the write cycle is a combination of the continuous current plus these bursts (which presumably are caused by the actual erase/write operations).

  • \$\begingroup\$ Sorry I have no idea how to interpret the above diagram. 1. What does D4-D1 indicate? 2. Why are there periodic dips( momentary glitches) in D4, D3 waveform? \$\endgroup\$ Commented Jan 11, 2022 at 7:27
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    \$\begingroup\$ The traces aren't well labeled. D4-D2 are the (digital) SPI clock and data lines. In this time frame each SPI transaction is so short that it looks like a glitch. If expanded you would see the individual clock pulses and data bits. It seems that the eeprom is being polled at intervals of a few hundred us, to detect when the write is finished. \$\endgroup\$ Commented Jan 11, 2022 at 9:45
  1. Yes, the EEPROM datasheet says that it consumes max 1mA while constantly reading from it, and max 3mA during a write cycle which can last up to 5ms, it does not even matter if you write a single byte or full page, as internally the EEPROM has to power the internal voltage generators for the full read-erase-program cycle.

  2. Digital signal transitions communicating with chip takes energy, and internal EEPROM erase-write cycle to store the data takes energy. Two completely different things.


digital ICs only consume power during state transitions

This is wrong in general. CMOS logic gates consume most of their power during transitions on their inputs. A EEPROM IC:

  • may have components other than logic gates (e.g. charge pumps) which consume power differently
  • has leakage currents in idle state which may or may not be significant
  • may generate transitions internally (e.g. may have internal clock signals) without any changes on the IC pins

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