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There is a clock (pulse generator) and a component or a model will increase its output 10 mV at each rising edge of the pulse generator. In other words the black waveform will generate the green one below:

LTspice

How can this be done?

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    \$\begingroup\$ Does this need to be a real circuit? or just for simulation. Also does the sequence have to repeat? \$\endgroup\$
    – Voltage Spike
    Jan 11, 2022 at 23:17
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    \$\begingroup\$ Just for simulation in LTspice not a real circuit. \$\endgroup\$
    – GNZ
    Jan 11, 2022 at 23:18
  • \$\begingroup\$ There you go... \$\endgroup\$
    – Voltage Spike
    Jan 11, 2022 at 23:26
  • \$\begingroup\$ The clock should be trivial to generate \$\endgroup\$
    – Voltage Spike
    Jan 11, 2022 at 23:26
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    \$\begingroup\$ It's called a staircase generator and I recall the RCA datasheet circuit that had an error in Electronics 301and I was the only student who fixed the design error, The TA couldn't care less \$\endgroup\$ Jan 11, 2022 at 23:43

5 Answers 5

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How can this be done?

If you just want to do this in a simulation, then use two voltage sources, a PWL and a clock voltage source.
PWL(0 0 0.1 0 0.1000001 0.1 0.2 0.1 0.2000001 0.2 0.3 0.2 0.3000001 0.3 0.4 0.3)

enter image description here

If it needs to be a circuit, you could have an op amp integrator that turns on during the rising edge and increases the voltage of the integrator only during the rising edge of the clock.

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  • \$\begingroup\$ Thank you! I think this is adequate for my purpose. I wanted to simulate a programmable DAQ board which increases its analog output for each trigger input. \$\endgroup\$
    – GNZ
    Jan 11, 2022 at 23:29
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    \$\begingroup\$ @GNZ Are you sure this is the solution to your problem? You seem to say you have a clock and you need a block that transforms that clock into the staircase waveform. As I see it, this solution provides a fixed, unalterable staircase. (BTW, instead of 0.100001 you can write +1u, and it will be relative to the previous point, be it data or time point; it's also a bit more readable) \$\endgroup\$ Jan 12, 2022 at 10:54
  • \$\begingroup\$ @concerned Yes what you described is exactly what I needed. But this was the closest answer so far. I would like a clock input generate that staircase for simulation in LTspice not a real circuit. \$\endgroup\$
    – GNZ
    Jan 12, 2022 at 12:15
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    \$\begingroup\$ @GNZ Then you shouldn't just accept the answer based on a "feeling". I'm saying this not because of a grudge against Voltage Spike, but because in the future, when other people will search for similar problems, they will see this question with an accepted answer, but it's not what the problem needs, so it will be confusing. Please note I'm also not dismissing the answer. \$\endgroup\$ Jan 13, 2022 at 17:54
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Since you're dealing with a clock input, it makes sense to have an integrator, as suggested by @user287001, but not analogic: "digital"1. In SPICE, the easiest method is with a tline, or ltline, but that only takes care of the delay, not the hold value, so you'll need to use the samplehold, as suggested by @bob_monsen, but not with a ramp input. You'll also need to specify whether you need a reset, or not, since the values will accumulate forever. Presuming you do, this is one way to do it:

test

A1, A2 are two sampleholds clocked in antiphase, forming the shift register. A4 is the [SpecialFunctions]/mota and it makes use of the multiplying input. The output of A1 is inverted and passed on to A2, which takes the inverted signal back to the inverting input of A1. This achieves a basic integrator (y[n]=x[n]+y[n-1]). A4 has two roles: to invert the signal (which could have been achieved by feeding the inverting input of A2, same thing), and to provide a reset through the help of the external signal given by V2. This signal needs to be at least 1 period long (to ensure that the clock samples the zero) and its values must be strictly 0 V or 1 V. If in doubt of this last requirement then add a buffer, similar to A5, whose purpose is to ensure 0...1 V logic, so that the integrator's "steps" are a multiple of 1. The output VCVS properly scales the signal and adds buffering. If a stiff voltage source is problematic, copy-paste the mota and add a proper gain, e.g. g=+/-10m (depending on which input you're using). If the 1 Ω value of rout is too large, make it less and compensate with the gain. Not lastly, since the input is already a clock, A2 provides the complementary outputs for the shift register but take note of the td=10u. The input signal has 1 μs rise/fall times, A5 has no settings (its rise/fall times will be determined by the solver's timestep). But the td (delay, see the help under LTspice > Circuit Elements > A. ... for more, or the ltwiki for more) ensures that the clock is delayed enough so that the samples don't fall on the edges. Depending on your application, you may wish to add tau and tripdt, as temporal helpers.


1SPICE is an analog simulator at its core, so any so-called "digital" gates are nothing but analog interpretations (the solver doesn't just calculate the states, it will calculate the transitions, too). There are mixed signal simulators, but LTspice is not one of them.

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    \$\begingroup\$ I see now I forgot to mention one thing: in the picture, the cursors show a value of 90.000011 mV, instead of a "clear" 90 mV. You should expect to see that at every step since the scaling factor used in the VCVS, -10m, is not a number that can be accurately represented in binary. This is a known problem. Using .opt numdgt=7 plotwinsize=0 will not cure this, neither will tweaking the *tol settings. \$\endgroup\$ Jan 14, 2022 at 9:07
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Version 1: Clock pulses advance a counter, the counter output is the input of a DA converter which outputs 10mV/unit.

version 2: There's an integrator. It gets generally 0V input, but each clock pulse triggers a pulse generator which ouputs a pulse which charges +10mV to the integrator

version 2 must be zeroed regularly, because integrators drift due leakage and opamp offset errors.

In simulators you may use an ideal integrator which does not drift. In addition you can use controlled sources, so charge a capacitor with a controlled current source. Control it with a pulse which is the difference of the clock pulse and a delayed version of the clock pulse.

If one knows the simulator well enough he may see how to describe it as a function (=script). I must unfortunately skip that route.

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There is a 'time' variable you can use in a behavioral voltage source voltage specifications, along with floor(), to do these sorts of things. See the help under "Waveform Arithmetic" for more information.

You can also use the sample and hold model (in special functions) to do it, with a ramp as input. Here is a web page description of using it https://forum.allaboutcircuits.com/threads/sample-and-hold-ltspice-simulation.165414/

Finally, you can create an arbitrarily long PWL file. Here is a python3 program you can use to generate something like what you want. Copy the output into a file, then use that as the PWL file in a voltage source. You probably will need to tweak it to output exactly what you want.

START_VOLTAGE = 1.0
END_VOLTAGE = 5.0
STEPS = 10
TOTAL_TIME = 1.0
RAMP_TIME = .0000001
STEP = TOTAL_TIME/STEPS
VSTEP = (END_VOLTAGE - START_VOLTAGE) / STEPS

for i in range(STEPS):
    # each step starts at 0, goes to i*INCREMENT, comes back to zero
    print(f"{i*STEP} 0")
    print(f"{i*STEP+STEP/2} 0")
    print(f"{i*STEP+STEP/2+RAMP_TIME} {START_VOLTAGE + i*VSTEP}")
    print(f"{(i+1)*STEP-RAMP_TIME} {START_VOLTAGE + i*VSTEP}")
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have a simple linear voltage ramp with time. Connect a voltage-controlled switch between this and a capacitor (try 1 uF or 1 nF). Use a PWM clock with very low duty cycle (ns) to periodically close the switch. This will sample-and-hold the ramp signal.

If the PWM starts with a 'high' value, then the capacitor will be initialized correctly, else use an initial condition on the capacitor.

You can use the staircase to directly control other circuits if they don't put a load on the capacitor; else use a voltage-controller voltage source (VCVS) with a gain of 1.00 to buffer it.

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  • \$\begingroup\$ This only works with a fixed clock frequency, however. \$\endgroup\$
    – Hearth
    Jul 23, 2022 at 23:13

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