I'm working with a device which will use Lithium thionyl chloride (non-rechargeable) batteries as a backup source; their discharge curve is quite flat and AFAIK you can't tell how is the battery in terms of whether it's good or about to die (EOL) unless you apply a dummy load. There are other more complex methods but my application requires me to save every penny and the client just wants to know if the battery is good or dead. Now the circuit is working but I would like to make sure If I'm actually doing it correctly or outright far from the right path.

My concerns:

  1. If this method of applying a dummy resistor when needed and measuring from the ADC at that time a legit method?
  2. If I should be concerned that the voltage divider and the ADC might eventually drain the battery, I added a MOSFET to cut off or connect the path between the battery and the voltage divider and ADC.

enter image description here

  • \$\begingroup\$ What happens if VDDSYS goes to zero as when power is removed? \$\endgroup\$ Jan 12, 2022 at 19:55
  • \$\begingroup\$ What happens when you have a passivated cell? \$\endgroup\$
    – Lior Bilia
    Jan 12, 2022 at 20:08
  • \$\begingroup\$ @KevinWhite I'm using an automatic backup IC TPS3619, VDDSYS is the output rail which either get supply from main supply VDD or in case of a power outage from VBCAP ; so in essence VDDSYS is mostly working in either states. I hope that answered your question. \$\endgroup\$ Jan 12, 2022 at 22:03
  • \$\begingroup\$ @LiorBilia It is mostly out of the scope of the device to identify if the battery is passivated or not. The client would most probably measure the battery and if passivated would be instructed to put on a dummy load for 1 minute maximum I suppose. \$\endgroup\$ Jan 12, 2022 at 22:06
  • 1
    \$\begingroup\$ @Sultanpepper - Ok, that would be ok. During a power outage there will be a slight bias for the P-FET due to the voltage drop across D27. You need to be careful about its threshold voltage. \$\endgroup\$ Jan 12, 2022 at 22:09

2 Answers 2


That solution is good. A couple of points.

  1. When on backup the P-FET will be biased on slightly by the voltage drop across D27. The threshold voltage of Q5 needs to be significantly higher than that to ensure it can be switched off properly.

  2. When powered normally the VDDSYS should be no lower than the voltage when on backup or again Q5 may turn on.

  3. I would add a capacitor across R90. The input of the ADC of the MCU will probably be equivalent to a capacitor of about 20pF charged to zero volts when the voltage is sampled. This has to charge through R190 in parallel with R106. The voltage will drop for a short time when sampling. There is normally a maximum source resistance of 5-10k ohms defined in the MCU data sheet. You are just within acceptable range but capacitor of a 1000pF or so will speed up the sampling and also provide a bit of filtering that may be desirable. Make sure the software does not attempt to read the voltage too quickly after Q5 is enabled.

  4. If you have a GPIO available it would be useful to provide separate control for Q5 and the load resistor R92. You can then read the voltage with a light load and a heavy load to better determine the battery condition.


The recommendations in the answer from Jonathan S. are also worth including. If the ability to check the battery at light load as well as heavy load is required T5 can be left in the circuit and R56 connected to the battery positive instead of VDDSYS. That will reduce any sensitivity to Q5 threshold voltage.

  • 1
    \$\begingroup\$ It may be worth combining @Jonathan's answer and this one by returning R56 to the battery positive rather than VDDSYS to avoid the issue with the threshold voltage of Q5. \$\endgroup\$ Jan 12, 2022 at 23:33
  • \$\begingroup\$ Thank you sir for the help, really appreciate it \$\endgroup\$ Jan 13, 2022 at 0:00

You can actually save quite a few more components in the circuit while simultaneously improving it: Remove T5, R56 and R58. Then connect the gate of Q5 directly to the collector of T7. You already have signal there that's perfectly suitable for driving Q5's gate. Additionally, this avoids weird interactions between the level of VDDSYS and Q5's threshold voltage, making the circuit more robust.

You should also decrease the value of R95 - you're overestimating T7's beta in saturation. A value of 2k2 would be more appropriate. This then asks T7 to deliver a current gain of 20, which is realistic for a saturated small-signal NPN transistor.

Other than that, the circuit is perfectly fine, including your choice of transistor for Q5 (DMP1555).

Including Q5 to disconnect the voltage divider is also very good idea.

  • \$\begingroup\$ Thank you sir for the help, really appreciate the time and effort you put in sharing your thoughts and knowledge, god bless \$\endgroup\$ Jan 13, 2022 at 0:01

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge that you have read and understand our privacy policy and code of conduct.

Not the answer you're looking for? Browse other questions tagged or ask your own question.