it seems that we can also use a frequency divider, e.g. a divide by 2
The disadvantage of dividing the frequency (for systems that use frequency modulation) is that when you divide the carrier frequency, you also divide the frequency deviations and, eventually, you reach a point where the number carrier cycles per logic "1" bit becomes exactly the same as for a logic "0" bit i.e. it fails to work.
The following picture hopes to show that dividing by 2 reduces the detection window available in the receiver's demodulator (called "space filter" and "mark filter" in the picture below): -
Clearly, dividing by 4 reduces the space and mark filters by another factor of two.
Image taken and modified from this site and from this document specifically. As you can see, for each division by two the mark and space filters required by the demodulator gets tighter and tighter to implement. This inevitably requires more complication if things start to get tight. There are some chips that do this; I've used them when demodulating 400 MHz where the chip in question implemented a divide by 4 before using a mixer. Not ideal but, a divide by 4 didn't degrade what we needed to implement.
It was a high speed data link with an FSK/FM deviation of about 15 MHz for a very bespoke aerospace application.
Some example numbers
If the centre frequency is 1 GHz and the data rate is (say) 100 kbps, for a maximum FM deviation of 100 kHz (for example), you would naturally expect to see an average of about 10,000 cycles of carrier per bit. For a logic "1" data bit this might be 11,000 cycles and for logic "0" it might be 9,000 cycles.
So, if you divided the raw modulated carrier by (say) 1,000, you'd get 11 carrier cycles for a logic "1" and 9 carrier cycles for a logic "0". In other words, you haven't got a big count difference between the two logic levels. If you decided to divide by 10,000 you wouldn't be able to distinguish between logic "1" and logic "0" at all.
Clearly if you divided by 100 instead, you'd count 110 cycles for logic "1" and 90 cycles for logic "0" and that is a more reliable count difference.
The bottom line is that each division is degrading the signal compared to superheterodyning the original modulated carrier down to a lower frequency because, the spectrum width of the down-converted signal remains exactly as it was at 1 GHz.