# Why must VOH > VIH and VOL < VIL for a combinational device?

I understand why VOH > VIH and VOL < VIL for a sender/receiver relationship between component A and B. In order for the receiver (component B) to be compatible with the sender (Component A), if VOH of B < VIH of A, then an input voltage between VOH and VIH cannot be interpreted by A.

However, I do not understand why VOH > VIH and VOL < VIL for the transfer voltage characteristic of a buffer (A single component), according to this website (https://computationstructures.org/notes/digitalabstraction/notes.html, under section 5.5 and 5.6). It states that

Note the dimensions of the rectangular gap between the shaded regions: its width is Vih−Vil, and its height is Voh−Vol. The height is necessarily greater than the width, since the height includes our noise margins Vil−Vol and Voh−Vih that are excluded by the width.

From my understanding, the transfer voltage curve just plots Vout vs Vin of a buffer. Why can't I just define my buffer to have V1OH < V1IH and V1OL > V1IL? Then any other components that wants to connect to my buffer needs to have V1OH > V2IH and V1OL < V2IL

I also referred to similar questions but I still cannot understand what is happening here:

Thresholds in Static discipline

Why VOH > VIH and VOL < VIL?

I am a non-ECE student that is self-studying the subject, so forgive me if I made any conceptual errors.

• Because it makes things a pain in the ass to keep track of and arbitrarily adds unneeded confusion. Your device also now cannot communicate with another of its kind. It's like having every screw on your machine be a different size even when there is no reason for them to be different and they could be the same. Jan 17, 2022 at 16:13

When designing a digital circuit you need a definition what voltage levels represent the HIGH vs LOW state, and every output must provide voltages that conform to that definition.

For a single line, the input receiving the signal must clearly understand the output voltage level:

• The input understands any voltage greater than VIH as HIGH, so we have the requirement that the output's HIGH must be produced as a voltage VOH greater then VIH, otherwise understanding HIGH gets unreliable.
• The input understands any voltage less than VIL as LOW, so we have the requirement that the output's LOW must be produced as a voltage VOL below VIL, otherwise understanding LOW gets unreliable.
• Whenever the output produces a voltage between VIL and VIH, the input doesn't know how to interpret that, and the results are unpredictable.
• Inputs typically allow a limited time span for the transition between valid LOW and HIGH voltages. If the transition is too slow, bad things like oscillation might happen.

When designing a complex circuit, you don't want to examine the data sheets for each and every input and output, you assume that they all obey common "family" conventions. So, while technically the buffer's VIL and VIH are irrelevant for its output VOL and VOH (unless you connect the output back to the input of the same chip), you can see them as representative for all logic gates on your board.

Most of the time, digital chips are designed in a way that makes them compatible with a broad range of chip families (as long as you don't mix supply voltages like 3.3V and 5V). But if you want to be super-safe, check the output specifications of every single signal line against the input requirements of the receiving chips.

Why must VOH > VIH and VOL < VIL for a combinational device?

It's generally accepted that for most CMOS logic devices (that run from a single power supply rail and 0 volts), that the output voltages it can produce will be close to the power rails and hence, the value of VOH will naturally be greater than the threshold level at the input (VIH).

Having said that, there is no golden rule and, some logic devices will level-translate. In these cases, VOH may indeed be less than VIH.

Take for example a normal run-of-the-mill CMOS device like this: -

Image from here and, as you can see, VOH (about 5 volts) is greater than VIH (about 3.5 volts). But, it could be a buffer that converts CMOS to TTL levels (concentrate on the output first): -

So, conceivably the output voltage (VOH) could be as low as 2.7 volts (TTL compatible) but with a CMOS level compatible input range: -

For simplicity, part of the assumption this chapter is working of is a family of devices, all with the same Vil and Vih, and any of which can be connected to any of the other devices in the family. So Voh > Vih because Vih is also assumed to be Vih of the device receiving this one's output.

You can, of course, do things differently, and sometimes you have to cross boundaries between different technologies — let's just say the book hasn't gotten there yet.

These Vil/Vol/ViH/ViL have different level to provide better noise margin in digital communication systems

Noise Margin:

Noise margin is a crucial concept in digital electronics that measures the tolerance of a digital system to variations or noise in the transmitted signal. It is the difference between the minimum input high voltage (Vih) and the maximum input low voltage (Vil) for a logical high level. A positive noise margin ensures that the system can withstand variations in the input signal without leading to misinterpretation of logical levels.

The formula for noise margin is given by:

Noise Margin = Vih−Vil

A higher noise margin provides better immunity to noise, ensuring reliable signal interpretation in the presence of signal distortions or fluctuations.

Example:

Let's consider an example with the following voltage levels:

Vih = 3v,Vil = 2v,Voh = 4v and Vol =1v

The noise margin for a logic high is determined by subtracting the input high voltage (Vih Vih) from the output high voltage (Voh Voh), calculated as Voh − Vih = 4 − 3 = 1

This means there is a 1-volt noise margin for a logic high.

For instance, if the sender transmits a 4-volt signal and it gets corrupted by a 1-volt noise signal, the receiver can still accurately interpret the signal as a logic high. This demonstrates the system's ability to tolerate and recover from noise, ensuring the reliable reception of logical levels even in the presence of signal disturbances.