I'm trying to build a simple fpga logic analyser and wondering how to best design the input circuit.
I would like to support 8 channels, voltage between 0-5V, with a adjustable threshold range (lets say between 0.7V~2.8V) connected to 3.3V tolerant pins. Not sure what frequency I can hope to achive, as high as possible I guess...
Since I'm fairly new to electronic I'm not sure exactly how to approch this,
My first idea was to use something like a LP38500TS adjustable linear regulator for the threshold, connect that to the inverted input of a comparator and my input signal to the non-inverted and set VCC to a value higher than 5V and then have a voltage divider after the comparator to bring the signal down to 3.3V...
Tried it in ltspice and it looked ok... :) But I have a feeling that there are much better ways of doing this.
- Will this design even 'work' in the real world?
- What would the easier/better/saner design be? (I'm sure there is one…). Wouldn't surprise me if I'm making this more complicated than it really is.