I am designing a board based on STM32F7 with a dozen of Digital inputs that need to be 12V tolerant. On the first design, I was using a voltage divider to have the right logical high detection when 12V is applied to the input. In addition to this, I added external pull-ups / pull-down manually soldered based on the configuration needed.

I wonder if I could use the internal pull-ups/pull-down of my microcontroller to do this. The problem is that those resistor (40K for the STM32F7) will also create a voltage divider with my voltage adaptation circuit and I think it won't work.. Here is an update with the schematics of the current adapter :

GPIO Voltage Adapter

Maybe I can use two OP-amps in inverting mode to drive the voltage from 12V to 3.3V but it will cost a lot of space on the board. Another solution would be to add a follower OP-AMP at the end of the voltage divider like this : GPI Voltage divider with buffer

Do you have any idea on how to do this ? Is their a simple solution to acheive this ?

  • 3
    \$\begingroup\$ Can you please explain what kind of dividers you now have, draw an example what you have and what you suggest, including the resistance values you are using. As it is now, it's hard to answer if it will work or not. \$\endgroup\$
    – Justme
    Jan 19, 2022 at 10:00
  • \$\begingroup\$ I am sorry, see my edit. \$\endgroup\$
    – Marech
    Jan 19, 2022 at 10:35
  • \$\begingroup\$ I think (maybe I am wrong) that all the solutions you show are overkill. A simple divider can suffice. If your MCU lacks internal protection diodes (unlikely) you can add them externally, perhaps with a small cap to eat spikes. \$\endgroup\$ Jan 19, 2022 at 10:42
  • \$\begingroup\$ With 'right logical high detection', do you mean that this circuit would need to trigger the STM pin at a certain input voltage? You could just clamp down the 12V input signal with a series resistor and a zener diode to ground. Thats only two cheap parts. Also has the benefit of not relying on the positive supply to sink/source current in order to limit input voltages. \$\endgroup\$
    – Thijs
    Jan 19, 2022 at 10:42
  • \$\begingroup\$ electronics.stackexchange.com/questions/359434/… The related listings go over something that might work for you. Thanks! \$\endgroup\$
    – Thijs
    Jan 19, 2022 at 10:54

3 Answers 3


There are multiple ways to do this and, as others are suggesting, clamping down the input signal in case it goes above 3.3V seems like the way to go. To add to existing answers, I suggest a more simple circuit for this that might be useful for your application. I'm also assuming the MCU is working on 3.3V

The datasheet for stm32F745 - STM32F746 datasheet state that a high level IO is recognized at a minimum of 0.7Vdd, so this amounts to 2.31V (https://nl.mouser.com/pdfdocs/DM00166116.PDF table 57 p.142) If we clamp between this and Vdd+0.3 (to avoid damage to the pin) we are good. A 3V zener is selected for this. Even with tolerances it will not conduct before the IO pin is meeting the high-level criteria, and also not let the voltage on the pin go high enough to damage the mcu. As long as the current trough the zener in OV and UV situations is low enough the zener voltage should not drift too much. R1 will make sure this is the case.

enter image description here

Rpu and Rpd are the STM32 IO pull up and pull-down respectively. Notice that the tolerance on these resistances are fairly large, but no matter. Lets say you have the pull-down enabled, which has a lowest value of 30Kohms (table 57). The high level IO criteria of 2.31V would be reached at 2.70V or higher input voltage.

Now lets say you have the pull-up enabled, the input-low criteria (0.3xVdd or 0.99V) becomes interesting. This is criteria can be met (again assuming 30K PD) at input voltage of 0.6V or lower.

Please check if these levels work for you. The benefit I find in this configuration is that the clamping of the input voltage does not require any current to be sunk by the positive supply rail. Some circuits can not tolerate this. If this sunken current has now way to go it might affect the supply voltage. Depending on what you are building this might not be a problem at all, but still interesting to consider.

The capacitor is just there for some filtering. You might not even require it. So a two-component solution might work for you. Just note that when the zener is used to clamp negative input voltages, its diode drop will be higher then that of a schottky diode, and this could cause the mcu pin diodes to ground to start conduction before the zener can. The resistor will in this case also limit the current to avoid damage. If these negative voltages can be common occurance, you can add a schottky to this arrangement in parallel to the zener to take care of the negative-going signals better.

The smaller you select the series resistor, the lower the impact of the PU and PD resistors on the minimum and maximum logic voltage thresholds. This ofcourse at the expense of higher currents during voltage clamping


If I understand your requirement correctly, what you are looking for is a circuit that accepts 12V inputs with minimal loading that doesn't interact with the MCU internal pull-up.

Here's a circuit that accepts 3.3V inputs, but is tolerant to 12V (as much as 20V, even) as well. (simulate it here):

enter image description here

The FET will disconnect the input when the input voltage rises above 3.5V or so (the FET threshold is 1.5V.) You can adjust this by modifying the gate bias.

Here's an even simpler idea (simulate it here): enter image description here

The input is pulled low only when the diode is forward biased, otherwise it is pulled up. I would recommend the extra pull-up (about 10k) to make the high-state impedance lower so it won't pick up noise.


I've used a circuit similar to what you're doing many times. You were on the right track with your first circuit but it's a much smaller circuit.


simulate this circuit – Schematic created using CircuitLab

For a Vin of 12 V or so, diode D1 clamps the GPI voltage to the rail plus about 0.2 V, which is within typical logic IC limits. You should always check your part's datasheet but the voltage will be fine.

D2 clamps any negative voltage levels or transients to approx. -0.2 V, to prevent damage to GPI.

Although the MCU will have input voltage clamping diodes in parallel with these, this circuit stops any high-voltage levels or transients from reaching the IC pins and silicon. The cheap diodes have much higher current capability than the IC's diodes, so the overall circuit has a wider max. input voltage range.

The circuit will have the MCU's internal pull-up or pull-down resistor active. You state that both are 40-odd kilohms. The potential divider formed by R1 and this pull resistor would only drop approx. 5% of the voltage across it, which is well within circuit acceptable limits. For 20 kilohms, the divider drops approx. 10%, still acceptable.

Which leads to: check carefully for the tolerance on these internal pull resistors. The tolerance is often not stated in the datasheet and needs a lot of hunting or manf. enquiry to get it. When it is stated, typical pull resistors can be +/- 50%. If in doubt, design for this tolerance - do not calculate on a 40,000 ohm resistance.

R1 limits the diode current for sourced or sunk by the input voltage. The acceptable input voltage range can be calculated from the max. power R1, D1 and D2 can dissipate, giving a much larger capability for input voltage range than the signal range, when just using 0.1 W or so resistors.

  • \$\begingroup\$ I understand the approach of clamping the voltage instead of dividing it. I just need to check what will be the low voltage detection level on the input. \$\endgroup\$
    – Marech
    Jan 19, 2022 at 12:43
  • \$\begingroup\$ @Marech, as referred to in the answer, that's for you to calculate for your specific parts against your specific design requirements: input voltage range, the MCU's pull resistances with tolerances, the supply tolerance, the input resistor with tolerance, temperature range and max dissipation. Remember it's a Q&A site, not a free design house or personal tutorial. The answer shows the circuit and explains the principle in detail, which is what the site's answers do. You need to apply it to your particular situation. It's all there. \$\endgroup\$
    – TonyM
    Jan 19, 2022 at 12:50
  • \$\begingroup\$ There's a leakage path between 12V and the MCU supply. Did that ever cause problems? \$\endgroup\$ Nov 3, 2023 at 0:13

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