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I created Product Of Sum (POS) expression using a Karnaugh map, and now i have to create its circuit using only NAND and NOT gates.

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At the start, I created this circuit based on OR and AND gates:

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And then I replaced it all with NAND gates:

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After checking it in the simulator, both circuits work in a different way.

Is there any intuitive way to quick convert POS expressions to NAND/NOT gates?

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  • \$\begingroup\$ TIP: instead of trying to do all the changes, try one change and see that it is comparable during simulation. Then build to the final solution checking each modification as you go. The final NAND gate needs inverting by the look of it. That might be your error but, you provide no information that helps folk work this out. \$\endgroup\$
    – Andy aka
    Jan 23 at 11:05

2 Answers 2

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Intuitive is a matter of what works well in one's own mind. In this case, I can only illustrate one method that comes to my mind. (This isn't the only approach, though.) It's simply an algebraic one:

$$\begin{align*} y &=(x_1' + x_3\, x_4\, x_5)\:(x_1'\, x_2' + x_3\, x_4) \\ &=((x_1' + x_3\, x_4\, x_5)\:(x_1'\, x_2' + x_3\, x_4))''\tag{1} \\ &=((x_1' + x_3\, x_4\, x_5)'+(x_1'\, x_2' + x_3\, x_4)')'\tag{2} \\ &=(x_1 \,(x_3'+ x_4'+ x_5')+(x_1+ x_2)\,(x_3'+ x_4'))'\tag{3} \\ &=(x_1 \,x_3'+ x_1 \,x_4'+ x_1 \,x_5'+ x_1\,x_3'+ x_1\,x_4' + x_2\,x_3'+ x_2\,x_4')'\tag{4} \\ &=(x_1 \,x_3'+ x_1 \,x_4'+ x_1 \,x_5' + x_2\,x_3'+ x_2\,x_4')'\tag{5} \\ &=(x_1 \,(x_3'+ x_4'+ x_5') + x_2\,(x_3'+ x_4'))'\tag{6} \\\\ \text{Set } t_1 &=x_3'+ x_4'= (x_3 \, x_4)' \\\\ &= (x_1 \,(t_1+ x_5') + x_2\,t_1)'\tag{7} \\\\ \text{Set } t_2 &=t_1 + x_5'= (t_1' \, x_5)' \\\\ &= (x_1 \,t_2 + x_2\,t_1)'\tag{8} \\ &= ((x_1 \,t_2)' \,(x_2\,t_1)')''\tag{9} \end{align*}$$

From here you can see that you'll need two NOTs and five NANDs.

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First, what you call "product of sums" I think would be better described as "product of sums of products". I can think of many different intuitive ways of realizing those.

Convert to product-of-sums

I.e. expand the brackets then just do it with NAND gates:

\$y=\overline{x_1}\overline{x_2}+\overline{x_1}x_3x_4+\overline{x_1}\overline{x_2}x_3x_4x_5+x_3x_4x_5\$
Apply De Morgan's:
\$y=\overline{\overline{\overline{x_1}\overline{x_2}}\bullet\overline{\overline{x_1}x_3x_4}\bullet\overline{\overline{x_1}\overline{x_2}x_3x_4x_5}\bullet\overline{x_3x_4x_5}}\$
So use only NAND gates, 2 levels of them. In the first level you NAND the terms just as written, then you NAND the results. The negations after the ending and the NANDing of the results just forms an OR gate, so you realized the form easily. That's the general method of realizing disjunctive forms, and it is usually very easy to directly write this form directly from a K-map without your intermediate step.

Just build as written

Build the two (or more) sub-circuits which are already in disjunctive form as above, then use NOTs to convert NAND gates to AND gates - you only have to negate every sub-result before the third level.

Write something else

You said this expression was calculated by hand using a K-map. You can write other forms of it, for example, directly the disjunctive form, or the conjunctive "product-of-sums" form. I have not rewritten you specific example as a conjunctive form, but it's realization is very similar of the disjunctive forms', just using NOR gates.

Skip optimization by hand

Write down the minterms you want your function to have, and use algorithmic optimization, such as QMC. It will generate a disjunctive form that you can easily build as described above.

PS

If you are designing logical circuits, watch out for hazards! 2 level combinational circuits can only have static hazards, but more levels can add dynamic hazards too! The simplest just-solve-it-all way of getting rid of them is by adding clocked input/output buffers, but you can eliminate them via K-maps or QMC

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