I've been tasked with the design of a PCB for a CubeSat project in my univesity and I'm trying to figure out exactly how the layout and stackup of my board should be done.

The board I have to design is for power distribution, this means that on the board there will be mainly DC DC converters and an IC for battery management. I forsee that 4 layers will be needed.

For the design I must take into account the ECSS guidelines (European Cooperation for Space Standardization) and I've been studying the relevant standard. I'm extremely confused by few of the rules listed on the document, for example:

  • 7.4.3 point e) Tracks should not be routed on external layers.
  • point b) In case critical tracks are routed on external layers, they shall not be routed under components.

I guess this is to improve EMI and radiations immunity but it means that the stackup of the board can't be like the "standard" stackup (signals on external layers and internal GND/power planes) but must be something like the one below

Needed stackup

I understand the upsides of this stackup (two ground planes can be stitched together around the periphery of the board to enclose all the signal traces in a faraday cage, signals and reference plane very close to each other etc.) however I can't really imagine to place a via for each signal coming from every smd pad: it looks like a routing and signal integrity nightmare to me.

For example the feedback loop of a DC/DC converter must be routed as short as possible and going from the top layer to the middle one and coming back to the top layer doesn't sound very wise to me.

Also so many vias means many via stubs acting like antennas. Probably an hybrid stackup would be better (signals and ground on top layer) but then why not going with the "classic" stackup.

  • point a)Solder mask shall not be used.
  • 7.6 point a)Copper planes should have additional openings in a grid format.

Since outgassing it's a big issue in space applications, they forbid the use of soldermask and suggest to apply a layer of conformal coating after the assembly. Also they suggest hatched polygons in order to allow humidity to get out of the board easily.

These points puzzle me a lot since all the boards we're buying from the industries, rated for space, come with solder mask, no conformal coating and full polygons. Also I'll be probably soldering the firs prototype and I'm afraid that by having no solder mask the tin will flow away from the smd pads.

Do you think that a stack up with signals only on internal layer is feasible? Are via stubs and feedback loop length a reasonable concern at the frequencies at which the DC/DCs are working? Do you have experience with such design? Should I remove the solder mask completely or maybe only on few spots?

These guidelines don't really make sense to me but I can't play by my own rules without justifying them first to the team.

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    \$\begingroup\$ Do you have to adhere to these rules or are they merely guidelines ? You provide very good examples where going to L2 for a short interconnect makes no sense whatsoever. \$\endgroup\$
    – tobalt
    Jan 24, 2022 at 18:46
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    \$\begingroup\$ WE've built many boards for space, with solder mask and without special holes in ground or power planes to allow humidity to escape. These were for much more demanding applications than a typical cube sat - 8 years on orbit life being typical. And we sometimes achieve twice that. They all had conformal coatings. \$\endgroup\$
    – SteveSh
    Jan 24, 2022 at 20:43
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    \$\begingroup\$ And there was nothing different in the stackups we used from an aerospace application, except maybe for addional layers to accomodate greater trace separation. \$\endgroup\$
    – SteveSh
    Jan 24, 2022 at 20:45
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    \$\begingroup\$ Who is your customer? And I think the US's Goddard Space Flight Center (GSFC) has a number of good design documents available to the public. \$\endgroup\$
    – SteveSh
    Jan 24, 2022 at 21:16
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    \$\begingroup\$ And yes, a stackup with signals only on the inner layers is not only possible, but may be preferred. That is our standard approach. On most boards, the only traces on the top layer are for short traces to allow connections from pads/pins to vias going down to internal layers. \$\endgroup\$
    – SteveSh
    Jan 24, 2022 at 21:35

1 Answer 1


I suggest without IPC, & HPC & SMPS DRC guidelines and experience that this may be an expensive lesson in repeat layouts and prototype costs with trial and error.

You will need a mentor to guide you in this process but I would strongly urge you hire a good fab shop to make this design for you after you perform a proto build with exposed traces and simulation runs.

You will need to consider via-in-pads and blind or buried vias and design for test (DFT) vias. Fortunately laser holes and small drill vias are possible but for thermal reasons epoxy filled vias are necessary and costly.

My best advice is have Sierra Proto Express do the final layout. I have had nothing but excellent support in the past when I had several other excellent shops like Tektronix in Colerado. enter image description here

Reference books from Sierra - Proto Express.



You may also need to consider shielded inductors which have a lower SRF and orientation relative to other exposed parts must not create a positive feedback.


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