Usually I dislike water analogies for electricity, but...
The clock on synchronous logic is sort of like a well-water pump. The pumping action is not continuous, it happens in bursts. When you lift the pump arm up, the pump inhales a little bit of the water from down below, and when you force the pump arm down again, it expels that water upstream. Move the pump arm up and down repeatedly, and it can move quite a lot of water upstream. Stop with the arm up, and nothing more happens. Stop with the arm down, and nothing more happens.
There is also an optimal pumping speed (this is also true for synchronous logic circuits). Pulsing the pump too slowly, loses momentum, so the water pressure and speed don't reach their full potential. But pulse the pump too rapidly, and the water just can't move into the impeller quickly enough. The metaphor breaks down a little, because circuits don't have viscosity...
In synchronous circuits, we have so-called digital circuits, which are really analog circuits pretending to follow the nice clean digital design rules. Digital circuits have a feature called "noise immunity": a logic high or logic low level is a range of voltages. As far as a digital designer is concerned, there's no meaningful difference between a logic high of 2.6V and 2.8V, as long as it's within the VIH voltage range the input is guaranteed to treat it as a logic high level. But the underlying circuit is made of transistors, and whenever it switches between high and low levels, it has to slew through all of the voltages in between. Real circuits do not switch instantaneously. So there is some finite period of time required for the signal to settle down to the correct value. That time period is called propagation delay. Add up all of the propagation delay times of all of the various combinational logic circuit elements that the signal has to go through, and that determines the shortest (fastest) clock period the circuit can tolerate. Operating at a faster clock speed will not allow enough time for the internal combinational logic to always reach the correct value. It always has some value, it's just not guaranteed to be the correct value until after the entire propagation delay time has passed.
There are a lot of factors that determine the required propagation delay time. Some of it depends on nominal design values, like the capacitance loading, and wire resistance, and things like that. Those factors depend on the laws of physics, the shape and dimensions of the materials, and other material characteristics, and temperature; so we can estimate propagation delay. But in manufactured devices, there are small variations from one unit to another. In the 1970's these manufacturing tolerances were not as tight as they are today, but there is still some amount of unpredictable variation from one device to another. So this led to a computer hobbyist trend called "overclocking", which is very much what you seem to be asking about.
Overclocking enthusiasts basically took a small risk by modifying their own personal computer to run at a higher clock rate, for example running a 6MHz CPU at 8MHz. It's not guaranteed to work. And it's also not guaranteed to fail in an obvious way either, which might be worse than if it just didn't work right away. If you were running a big simulation, and there was some small undetected calculation error that only happens after it's been doing a bunch of big calculations and got a hot spot, then you might not know that you got a bad result. On the other hand, if you were just using it to play games, there's no harm done. However, even a hack like overclocking still has to provide a constantly-changing clock input. Simply connecting the clock input always-low or always-high is not some magical, free hyperspace bypass -- I assume you already knew that, but were just trying to learn why it doesn't work that way.
Here's a little more detail about what the clock signal actually goes into. The simplest idea of a synchronous logic circuit would be a finite state machine, made of some "D" flip-flops and some logic gates. All of the D flip-flops receive the clock signal. The outputs from the flip-flops drives the inputs of the maze of logic gates, and the outputs from the tangled mess of logic feed back into the inputs of the D flip-flops. So there is a kind of feedback loop, but the flip-flops interrupt that feedback loop by imposing a timing discipline. The flip-flop pretty much ignores whatever happens on its data input, until just at rising edge of the clock, and then suddenly the outputs are changed to match the value of the inputs. This happens very rapidly, ideally it's like taking a snapshot of the input and driving that value continuously for the rest of the clock cycle. If the flip-flop kept updating its outputs to match its inputs continuously for as long as the clock input was high, that would not be a flip-flop; it would be a transparent latch. And we need flip-flops, not transparent latches, to build state machines. There's no change on the falling edge of the clock. Eventually the combinational logic determines a new value for the flip-flop inputs. But the only way that the machine "knows" that the new value has arrived, is that the clock rising edge happens. That's what drives the process of updating the register value, so that the rest of the logic can start calculating the next step. This is the basic principle of operation of all finite state machines and all other synchronous logic.