What happens if clock cycle is replaced with constant high voltage in a processor?

Would the data in registers change at light speed and maybe become unstable/undefined, or would the processor stop changing state altogether?

To give all the gates time to change state from the whole chain we use a clock. The clock is an input to the CPU switching between 0 and 1 (signal going low to signal going high to signal going low, etc.), that drives the CPU to perform operations.

If the clock speed is increased to 100GHz, a cycle will be 0.01 nanoseconds ... What happens when this size limitation is violated? What happens is that certain parts of your circuit are in the 'current' cycle, and other parts are in the 'previous' cycle. It gets really hard to handle such distributed systems.

But then this post says:

it will just stop

So I'm confused on the outcome.

If I picture a simple timer register hookedup to an adder, and each clock cycle its data gets ++1'ed, doesn't a constant high mean the register data loops through the adder and back to itself at light speed, adding to itself indefinitely? rather than stopping?

• exactly what happens depends on whether you're dealing with a dynamic or static processor, but either way it won't do anything useful. Jan 24 at 20:42
• light speed is not a measure of a time interval, unless a distance is specified Jan 24 at 21:22
• @user1850479 this is the part i'm trying to understand in more detail. What is the clock (0 or 1) fed into? is it an input to gates to potentially change their state based on their other inputs?
– Dan
Jan 24 at 22:32
• You can think of the clock as an input to gates that tells them it is time to update. If you stop telling them to update then they won't do anything. Jan 24 at 22:39
• A really good (if very long-winded) explanation of the basics of how the clock drives a digital circuit is given in Charles Petzold's 1999 book Code: The Hidden Language of Computer Hardware and Software I highly recommend this book if you want to learn how it all works from first principle. Jan 25 at 15:39

Your doubts arise from lack of understanding of the basics about synchronous sequential logic networks, of which modern CPUs and related basic blocks, like counters, are just particular examples.

As someone else already pointed out, such networks can change state only in consequence of a clock edge, i.e a clock signal transition.

I suggest you to investigate the basic behavior of edge-triggered flip-flops (i.e. 1 bit static memory, simplifying a bit :-) and other basic concepts about synchronous network timing requirements, such as setup time, hold time and propagation delay.

EDIT (To tackle some comments by OP @Dan)

• You keep mentioning the "speed of light", but you really should get that term out of your system.

Speed of light is a "speed" in physical sense, i.e. a ratio of space on time. Speed describes how fast physical bodies move. In digital logic we talk about processing speed, i.e. how many bit per seconds are processed.

Relating the two is not trivial at all (a bunch of charges moving is not necessarily the same as a bunch of bits "moving").

• Asynchronous (i.e. "clockless") logic is theoretically faster, because devices can react without waiting for the clock edge. This doesn't mean the single device is "infinitely" fast. With the same technology and the same circuit complexity, getting rid of the clock just saves you the time some of the clocked devices waste waiting for the clock edge when they already have their inputs "ready". This doesn't increase the speed with which a single transistor switch state. So you will still have propagation delays. (https://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_circuits).

OTOH, designing a complex asynchronous system is a timing nightmare, since any subsystem can react at any time, and you still have to meet setup and hold time requirements, but now you can't know when other blocks will switch their outputs since you have no synchronization signal. Moreover, you will still need synchronization, since some tasks will have to wait for other ones to complete. Without clock signals, this will be much more complex.

You could find this interesting:
https://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU.

• So the clock (positive or negative edge-triggered) is like an on off switch. Right when it turns on (or off), an action takes place and the result gets stored in a memory. The clock value could also be used to derive result value but the main point is to acts an as on/off switch. And it does so To give all the gates time to change state from the whole chain we use a clock. I guess it IS possible to design sequential circuits with memory without a clock, but it gets difficult to design as this post says electronics.stackexchange.com/a/66065, so designer just took the easy way?
– Dan
Jan 25 at 0:21
• i.e it IS possible to design sequential circuits with memory that work with light speed (no clocks) but it's easier said than done? I know that combinational circuits (like a simple OR gate on a chip) have no clock and just give you direct output based on input.
– Dan
Jan 25 at 0:27
• Yes, "asynchronous logic" is a thing. No, it's not light speed: the main constraint is the capacitance presented by the wires and driven gates. See "Elmore delay" for a simplified model. For more on async, see async.org.uk Jan 25 at 14:58
• @pjc50: A bigger issue with asynchronous logic is that it has no "nice" way of handling race conditions. If two tasks will need to do something with a shared bus, it will be hard to avoid either requiring that X wait for Y even if X would have been ready first, or that Y wait for X even when Y would have been ready first. Using synchronous logic makes it possible to ensure that both X and Y are in agreement as to Y was ready before X. Jan 25 at 20:34
• @Dan The term "propagation delay" combines two effects. There's transmission line delay, related to the speed of light (in the particular material, which is NOT the same as C, the speed of light in a vacuum). And ramp time, the time for a transistor output to switch between two voltages. Normally the circuit elements are close enough to each other that the rise and fall time is the dominant factor inside a computer processor. Get outside that chip, to a communications network, and the transmission line effects become very important. Jan 25 at 23:03

The clock must transition, from low to high, and repeat, in a regular pattern.

It is these transitions which drive changes in the logic, not the high level. No transitions = no logic change. So without transitions, it will stop working.

This includes "extra high" voltage (it will likely be damaged.)

If only static elements are involved, then operation will appear to completely "freeze" during the entire duration of the clock removal. Restart the clock, and it will pickup exactly where it left off (like no time had passed whatsoever.)

If dynamic elements are involved (likely today, such as watchdog timers, interrupt-on-change, DRAM memory refresh, etc.) then something will likely be missed or corrupted during a long clock pause. In the case of DRAM loss, the currently running code will now be garbage, so the processor will fault in short order from trying to run garbage code.

It is the transitions of the clock which signal to the processor to "do the next step." The low-high transition or edge (legacy), and also the high-low edge (modern) now both do something.

On today's modern processors, multiple cores with multiple threads means that each clock cycle is doing hundreds, even thousands of things in parallel on each clock edge.

Clock edges must be used, because they are sequential, and these edges must be separated by some amount of time, to allow the "step" to fully propagate or complete before the next is started. "Overclocking" is increasing the clock rate higher than the normal value. The typical clock rate includes a safety margin, so it is usually possible to increase this somewhat. Increasing it causes the processor to work harder, so commonly needs a slight boost in voltage to keep operating. But increasing the clock rate too much will eventually violate these step timings, especially over all possible temperature ranges.

• @Dan: a synchronous counter (like you'd find in your timer register) doesn't count when the clock is high (or low). It counts when a clock edge happens (either when the clock transitions from low to high or from high to low). Otherwise it wouldn't work at all - the clock stays high for a whole half cycle, and low for the other half. It would "count at light speed" like you say for half the cycle.
– Mat
Jan 24 at 21:00
• @Dan read up on flip flops. These are the basic building block of sequential digital logic. The clock is a bit like a machine with a crank handle. You crank the handle and something happens. No crank and nothing happens. Jan 24 at 21:27
• Yes, in an ideal logic system with a clock, state changes only occur on a clock edge. So if the clock stops, the system stays in its current state, forever, even if the inputs change. Though many systems have asynchronous resets that operate independently of the clock. Jan 24 at 21:32
• @Dan "fed into gates": yes .. inside the flip-flop. Not any of the other combinational logic. You can think of a flip-flop as a pair of latches, one of which is enabled on one half of the cycle and one on the other, so it can only change its output during the transition. Jan 25 at 11:34
• @Dan You're still missing the point. Actually calling it a "clock" should make this clear, because the voltage going up and down is identical in every way to how the pendulum of a clock moves backwards and forwards. If you stop the pendulum of a clock from going backwards and forwards, do the hands keep moving to count seconds? Clearly they don't. And nor does timer electronics keep moving if the voltage stops going backwards and forwards. Jan 25 at 15:38

Usually I dislike water analogies for electricity, but...

The clock on synchronous logic is sort of like a well-water pump. The pumping action is not continuous, it happens in bursts. When you lift the pump arm up, the pump inhales a little bit of the water from down below, and when you force the pump arm down again, it expels that water upstream. Move the pump arm up and down repeatedly, and it can move quite a lot of water upstream. Stop with the arm up, and nothing more happens. Stop with the arm down, and nothing more happens.

There is also an optimal pumping speed (this is also true for synchronous logic circuits). Pulsing the pump too slowly, loses momentum, so the water pressure and speed don't reach their full potential. But pulse the pump too rapidly, and the water just can't move into the impeller quickly enough. The metaphor breaks down a little, because circuits don't have viscosity...

In synchronous circuits, we have so-called digital circuits, which are really analog circuits pretending to follow the nice clean digital design rules. Digital circuits have a feature called "noise immunity": a logic high or logic low level is a range of voltages. As far as a digital designer is concerned, there's no meaningful difference between a logic high of 2.6V and 2.8V, as long as it's within the VIH voltage range the input is guaranteed to treat it as a logic high level. But the underlying circuit is made of transistors, and whenever it switches between high and low levels, it has to slew through all of the voltages in between. Real circuits do not switch instantaneously. So there is some finite period of time required for the signal to settle down to the correct value. That time period is called propagation delay. Add up all of the propagation delay times of all of the various combinational logic circuit elements that the signal has to go through, and that determines the shortest (fastest) clock period the circuit can tolerate. Operating at a faster clock speed will not allow enough time for the internal combinational logic to always reach the correct value. It always has some value, it's just not guaranteed to be the correct value until after the entire propagation delay time has passed.

There are a lot of factors that determine the required propagation delay time. Some of it depends on nominal design values, like the capacitance loading, and wire resistance, and things like that. Those factors depend on the laws of physics, the shape and dimensions of the materials, and other material characteristics, and temperature; so we can estimate propagation delay. But in manufactured devices, there are small variations from one unit to another. In the 1970's these manufacturing tolerances were not as tight as they are today, but there is still some amount of unpredictable variation from one device to another. So this led to a computer hobbyist trend called "overclocking", which is very much what you seem to be asking about.

Overclocking enthusiasts basically took a small risk by modifying their own personal computer to run at a higher clock rate, for example running a 6MHz CPU at 8MHz. It's not guaranteed to work. And it's also not guaranteed to fail in an obvious way either, which might be worse than if it just didn't work right away. If you were running a big simulation, and there was some small undetected calculation error that only happens after it's been doing a bunch of big calculations and got a hot spot, then you might not know that you got a bad result. On the other hand, if you were just using it to play games, there's no harm done. However, even a hack like overclocking still has to provide a constantly-changing clock input. Simply connecting the clock input always-low or always-high is not some magical, free hyperspace bypass -- I assume you already knew that, but were just trying to learn why it doesn't work that way.

Here's a little more detail about what the clock signal actually goes into. The simplest idea of a synchronous logic circuit would be a finite state machine, made of some "D" flip-flops and some logic gates. All of the D flip-flops receive the clock signal. The outputs from the flip-flops drives the inputs of the maze of logic gates, and the outputs from the tangled mess of logic feed back into the inputs of the D flip-flops. So there is a kind of feedback loop, but the flip-flops interrupt that feedback loop by imposing a timing discipline. The flip-flop pretty much ignores whatever happens on its data input, until just at rising edge of the clock, and then suddenly the outputs are changed to match the value of the inputs. This happens very rapidly, ideally it's like taking a snapshot of the input and driving that value continuously for the rest of the clock cycle. If the flip-flop kept updating its outputs to match its inputs continuously for as long as the clock input was high, that would not be a flip-flop; it would be a transparent latch. And we need flip-flops, not transparent latches, to build state machines. There's no change on the falling edge of the clock. Eventually the combinational logic determines a new value for the flip-flop inputs. But the only way that the machine "knows" that the new value has arrived, is that the clock rising edge happens. That's what drives the process of updating the register value, so that the rest of the logic can start calculating the next step. This is the basic principle of operation of all finite state machines and all other synchronous logic.

The clock synchronises operation of all inner components of any CPU. If it stops (or gets constantly high), the CPU should just stop too. At least 8051 microcontroller acts like that. It will definitely not "overclock" the CPU (aka. it won't work as fast as possible). All nasty side effects like clearing/changing of registers, undefined state etc. can happen too.

Clock stopped: if the registers and logic are static, the machine holds its state. If they’re dynamic, the state will eventually be corrupted or lost.

(Dynamic logic is used in some architectures to reduce area. Like DRAM, it needs to be cycling to refresh its state. It was more common in the NMOS era, though it still sees use in CMOS.)

Clock running beyond machine limits: unstable operation, as flip-flop setup times aren’t being met so their state isn’t predictable.

The basic cycle timing needs to be no less than the worst-case flop clock-to-output + routing delay + setup to the next flop stage.

There is also some restriction on clock high and low, as flops are composed of latches that activate on opposite clock levels: they need a minimum pulse time to propagate.