# PSFB - Asymetric current at the secondary

At the 3rd step of the PSFB cycle, the current at the secondary is not shared equally by the two windings that it would be if it were a full bridge. Does anyone can explain why it is not the case ? And why only the variation of the two output current is shared by the two windings ? I am not sure that the sign of the following pictures are correct. It should be Iout - deltaIout/2 and - deltaIout/2 as no energy is being transfered. I probably do an error ?

The same appears from this diagram :

This one seems to be better for the same architecture :

Have a nice day ,

------------------------------------E D I T --------------------------------

Well I have not still find the answer but by documenting my self I found something well weird :

Here is the simulation that "A concerned citizen" have done. (Thank you). It is a bit modified according to my needs and we clearly see a negative current :

Then I was looking something else and I found this comment on the video (linked below) ...

It seems to be pretty complicated to avoid a negative current with SR ... And I think it is right that it can do a voltage spike as there is no way for the current to go ... There is nothing to limit the rise of voltage when the current is negative...

I am probably missing something...

Here is the last simulation :

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TEXT -528 -40 Left 2 !.model sw sw ron=50m roff=0.1g vt=0.5 vh=-0.5 ; level=2 oneway ilimit=1k\n.model d d ron=50m roff=0.1g vfwd=0.45 vrev=1k epsilon=50m revepsilon=1
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TEXT -768 224 Left 2 ;tau = Output RC time constant
TEXT -776 256 Left 2 ;td = Output propagation delay
TEXT -528 -176 Left 2 !.param Fsw = 100k DELAB = 100n DELCD = 100n D=0.8 Lp = 1 Ns = 1 Np = 21 Ls = Lp*Ns**2/Np**2
TEXT -688 920 Left 2 ;Manque la simulation de DELAF et DELBE, utile pour diminuer les pertes
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TEXT 720 888 Left 2 ;2u
TEXT 2352 656 Left 2 !K2 L8 L9 L10 1
TEXT 2128 888 Left 2 ;2u
LINE Normal 192 1072 192 320 2


Have a nice day,

• Did you forget the link to the document? Jan 25, 2022 at 17:40
• You re right as usual :)
– Jess
Jan 25, 2022 at 18:21
• @aconcernedcitizen. Thank you for your simulation ! Could you please send it ? I will be really happy to better understand how you simulate a phase shift "controller". Then there is still a question why the current is not shared equally by the two winding ? Why each windings have just not "(Iout+deltaIout)/2" current value ?
– Jess
Jan 26, 2022 at 14:16
• There is also something which troubles me. It exists some PSFB without "syncrhonous" rectification at the secondaries, so when there are diodes instead of MOSFET/GaN how can the current be negative ?
– Jess
Jan 26, 2022 at 15:18
• @Jess The main reason is explained in the help (LTspice > Circuit Elements > E. ..., bottom note). In addition, I vaguely recall (can't remember where) that, due to the modified nodal analysis of LTspice, voltage sources that are off ground may cause problems (something about matrix inversion? I really can't remember). So the floating drivers should be better behaved. That's not to say all voltage sources are cursed, just that I'm playing it safe. The more complicated the circuit, the more chances there are that something will run amok -- no need for me to help that. Jan 27, 2022 at 18:29

(I need to make this an answer, to justify the copy-paste). You were right, congratulations for the detective eyes! Given the folow-up comments, I've added a separate section with diode rectification, and the plot shows the main difference between them. The missing bits to the right are the same as the middle part; it's just copy-paste:

I've also made a 3rd section with MOSFETs (and reduced load/supply; not shown in the picture above), which shows the same negative current in the rectification. There are some side effects, too, such as oscillating output (the MOSFETs have parasitics, the VCSW don't), high frequency oscillations (same parasitics + the coupling is not 1), but the overall shape is there. Here is the whole thing, sorry for the aspect, but it was cropped in a haste, and updated in a similar manner. The lines will make all the difference, I'm sure...

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WINDOW 3 36 40 Left 2
SYMATTR InstName L3
SYMATTR Value 100u
SYMATTR Type ind
SYMBOL sw 304 768 R180
SYMATTR InstName S5
SYMBOL diode 256 736 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D5
SYMBOL sw 80 768 M180
SYMATTR InstName S6
SYMBOL diode 128 736 M180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D6
SYMBOL Digital\\or -144 544 R0
WINDOW 3 -8 30 Left 2
SYMATTR Value tau=10n
SYMATTR InstName A9
SYMBOL ind2 112 528 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName La2
SYMATTR Value 10u
SYMATTR Type ind
SYMBOL cap 400 624 R0
SYMATTR InstName C1
SYMATTR Value 100u rser=10m
SYMBOL Digital\\or -144 640 R0
WINDOW 3 -8 30 Left 2
SYMATTR Value tau=10n
SYMATTR InstName A10
SYMBOL res 464 544 R0
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL sw 736 192 M180
SYMATTR InstName S7
SYMBOL diode 784 160 M180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D7
SYMBOL sw 736 304 M180
SYMATTR InstName S8
SYMBOL diode 784 272 M180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D8
SYMBOL sw 1168 192 R180
SYMATTR InstName S9
SYMBOL diode 1120 160 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D9
SYMBOL sw 1168 304 R180
SYMATTR InstName S10
SYMBOL diode 1120 272 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D10
SYMBOL ind2 896 208 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L4
SYMATTR Value 100u
SYMATTR Type ind
SYMBOL ind2 752 496 R180
WINDOW 0 36 80 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName L5
SYMATTR Value 100u
SYMATTR Type ind
SYMBOL ind2 752 640 R180
WINDOW 0 36 80 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName L6
SYMATTR Value 100u
SYMATTR Type ind
SYMBOL diode 784 416 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D11
SYMBOL diode 784 608 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D12
SYMBOL ind2 912 416 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName La1
SYMATTR Value 10u
SYMATTR Type ind
SYMBOL cap 1040 512 R0
SYMATTR InstName C2
SYMATTR Value 100u rser=10m
SYMBOL res 1104 432 R0
SYMATTR InstName R2
SYMATTR Value 10
SYMBOL ind2 -48 1072 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L7
SYMATTR Value 100u
SYMATTR Type ind
SYMBOL ind2 752 928 R180
WINDOW 0 36 80 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName L8
SYMATTR Value 100u
SYMATTR Type ind
SYMBOL ind2 752 1072 R180
WINDOW 0 36 80 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName L9
SYMATTR Value 100u
SYMATTR Type ind
SYMBOL ind2 768 960 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName La3
SYMATTR Value 10u
SYMATTR Type ind
SYMBOL cap 1184 1056 R0
SYMATTR InstName C3
SYMATTR Value 100u rser=10m
SYMBOL res 1248 976 R0
SYMATTR InstName R3
SYMATTR Value 10
SYMBOL nmos 688 1088 R0
SYMATTR InstName M1
SYMATTR Value IPB107N20N3
SYMBOL nmos 960 1088 M0
WINDOW 3 57 51 Left 2
SYMATTR Value IPB107N20N3
SYMATTR InstName M2
SYMBOL g 576 1152 R0
SYMATTR InstName G1
SYMATTR Value 12
SYMBOL res 624 1152 R0
SYMATTR InstName R4
SYMATTR Value 1
SYMBOL g 1072 1152 M0
SYMATTR InstName G2
SYMATTR Value 12
SYMBOL res 1024 1152 M0
SYMATTR InstName R5
SYMATTR Value 1
SYMBOL nmos 272 1088 M0
WINDOW 3 57 51 Left 2
SYMATTR Value IPB107N20N3
SYMATTR InstName M3
SYMBOL nmos 272 896 M0
WINDOW 3 57 51 Left 2
SYMATTR Value IPB107N20N3
SYMATTR InstName M4
SYMBOL g 384 960 M0
SYMATTR InstName G3
SYMATTR Value 12
SYMBOL res 336 960 M0
SYMATTR InstName R6
SYMATTR Value 1
SYMBOL g 384 1152 M0
SYMATTR InstName G4
SYMATTR Value 12
SYMBOL res 336 1152 M0
SYMATTR InstName R7
SYMATTR Value 1
SYMBOL nmos -256 1088 R0
WINDOW 3 57 51 Left 2
SYMATTR Value IPB107N20N3
SYMATTR InstName M5
SYMBOL nmos -256 896 R0
WINDOW 3 57 51 Left 2
SYMATTR Value IPB107N20N3
SYMATTR InstName M6
SYMBOL g -368 896 R0
SYMATTR InstName G5
SYMATTR Value 12
SYMBOL res -320 896 R0
SYMATTR InstName R8
SYMATTR Value 1
SYMBOL g -368 1152 R0
SYMATTR InstName G6
SYMATTR Value 12
SYMBOL res -320 1152 R0
SYMATTR InstName R9
SYMATTR Value 1
TEXT -376 0 Left 2 !.model sw sw ron=50m roff=0.1g vt=0.5 vh=-0.5 ; level=2 oneway ilimit=1k\n.model d d ron=50m roff=0.1g vfwd=0.45 vrev=1k epsilon=50m revepsilon=1
TEXT 392 336 Left 2 !k l1 l2 l3 0.99
TEXT 376 440 Left 2 !.tran 1m
TEXT 368 392 Left 2 ;.save v(o)
TEXT 1000 344 Left 2 !k2 l4 l5 l6 0.99
TEXT 1016 848 Left 2 !k3 l7 l8 l9 0.99
LINE Normal -48 816 -48 64 2
LINE Normal 624 816 624 112 2
LINE Normal 1376 816 -336 816 2

• Thank you so much ! I will take a look on it tomorrow :D I am wondering what is the man underneath "a concerned citizen". But you could answer : " This is not who I am underneath that defines me ... But what I do...." youtube.com/watch?v=WW1a_cNKapY. There is still the question : Why each windings have just not "(Iout+deltaIout)/2" current value ? I wil probably find the answer into your simulation :)
– Jess
Jan 26, 2022 at 18:18
• @Jess I have to confess that these beasts are new to me, and if I change values on the load side RLC, the VCSW and the MOSFET versions show results that differ in certain areas. What you say seems to be true for the diode rectification. I'll try to read and poke around some more. And underneath me is my neighbour, I'll send your regards... Jan 26, 2022 at 19:12
• I don't know what else to say, since no other answer came up, but I'm hoping you realize you're not looking where you need to look. In your 1st picture after edit (LTspice sim) the cursors are at the end, when the body diode conducts, but the 2nd picture you're showing below, from TI, with the yellow marks, points at the beginning (follow the arrow). That part that is zoomed in, pointed at with the 2nd arrow, shows that inverse conduction, where your cursors are, and they're due to the overlapping controls of the SR. Feb 3, 2022 at 18:58
• You re right ;)
– Jess
Feb 8, 2022 at 12:56