# Pull-up and pull-down resistor on one trace

Does it ever make sense to have both a pull-up and a pull-down resistor on the same trace?

Background:

I'm designing a backplane to follow the OpenVPX guidelines and I saw this rule

Rule 7-20: The backplane shall implement a 5% 220-ohm pull-up resistors to 3.3V_AUX and a 1.8K-ohm pull-down to ground on the SYSRESET* signal, or the Thévenin equivalent implementation, located at each end of the backplane.

Am I reading it right? Is it asking for both a pull-up and a pull-down on the same signal? Does this only make sense because the pull-down is a way higher resistance? What is the advantage of doing this instead of just having a pull-down?

• It's an odd way of specifying that you must implement a voltage divider on each end which applies 3V to that line, or alternatively use the Thevenin equivalent which would be a single 200R resistor to a 3V source - but only if 3.3V_AUX is present. Jan 25 at 17:32
• Ahhh Thanks. I totally didn't pick up that it's just a voltage divider. Jan 25 at 17:47

Yes, but one of the resistors is much smaller than the other. This has the effect of pulling SYSRESET* up to ~3V if 3.3V_AUX is present and down to ground in its absence.

This is a common solution to use 2 resistors in an array or use a single voltage to the Thevenin Threshold or for differential signals with the effective parallel resistance and a voltage divider.

In this case, 10% below Vdd makes an open circuit logic high but when connected to a driver is a 220/1k8= ~ 200 ohms termination for high speed with low ringing.. (=196)

Other: Although this is a primitive question, designing for OpenVPX beyond 10 Gbps is very non-trivial and choice of dielectric loss tangent and smaller layer thickness to achieve lower Zo with 3 mil tracks and laser vias in pads is quite non-trivial.

• One ought to review the patents of DAWN like drill-back on stubs or SynQor to appreciate the complexity of backplane design and have all the tools for VITA 68 S-parameter simulation models of signal paths.

There is more than meets the eye to backplane design > 10 Gbps.

Note: There is a ground plane with a small gap around each rectangular isolated pad for J10.

## Anecdotal

• When SCSI came out with 32 bits and dual-channel, the single resistor choice made more sense and was called the "Active Terminator" at the common-mode median voltage.

• If I wanted to send TTL signals a greater distance of delay than the fall time to avoid ringing then I would use an active voltage source of 1.4V (=TTL input threshold) and terminate with a single R to 1.4V (lower than the asymmetric TTL load impedance.) This is also the active threshold where the impedance of the receiver is the same for+/- noise. So choosing a net R single resistor or a pullup+down to match the character impedance Zo of the traces or cable results in minimal reflection waves that cause ringing back and forth or at one point going up and down. Even a rough approximation makes a significant improvement although reduces the fanout capability.

• I recall when the 68000 MOT CPU came out in the mid-80's with new relatively high-speed processing power, a great computer company, called Convergent Technology (CTI) in San Jose used this method to speed up the clock and data bus of the CPU to outperform all competitors using the same CPU. They made my favourite personal work-computer of all-time running CTOS.

The two resistor technique (pull up/pull down) is useful when 1) You're trying to terminate a signal line in it's characteristic impedance but 2) your driver does not have the strength to drive a trace terminated in, say 50 or 75 ohms to GND.

In that case, a pull up of 110 ohms and a pull down of 220 ohms would give you a thevenin equivalent termination of around 75 ohms, which in many instances would be OK, even with a 50 ohm trace.