I have been writing VHDL for a while. There, we have the concept of libraries, which comes in handy. I cannot find something of this nature in SystemVerilog.

Is it true that SystemVerilog has no concept of compiling modules into different libraries like VHDL? If so, what is the closest equivalent of VHDL libraries?

  • \$\begingroup\$ There is a concept of importing a package and including a header file. You may wanna look into it. \$\endgroup\$
    – Mitu Raj
    Jan 25, 2022 at 18:20
  • \$\begingroup\$ I have found that we can create a package and then use `include and import to bring it into the our module. However, that is not my question. \$\endgroup\$
    – quantum231
    Jan 25, 2022 at 20:34

1 Answer 1


One of the differences between VHDL and SystemVerilog is that other than the definition of compilation units and configurations, SystemVerilog stays away from tool specific aspects of the compilation process.

The concept of a library usually involves organization of data in a physical filesystem. Most tools that compile SystemVerilog also compile VHDL and allow you to target source code into in different libraries in similar manner. You should look at the Unser manuals for the tools you are using.

Section 33. Configuring the contents of a design in the IEEE 1800-2017 SystemVerilog LRM does provide a way to specify library behavior from within the language. But there is currently no other way within the language to indicate which modules belong to which libraries.

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    \$\begingroup\$ Libraries (VHDL) are not tool specific and have no relationship to how files are organized on the file system. They are closer to C++ namespaces. \$\endgroup\$
    – user16324
    Jan 25, 2022 at 18:51
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    \$\begingroup\$ @user_1818839. that's true for VHDL, but not so much in SystemVerilog. \$\endgroup\$
    – dave_59
    Jan 25, 2022 at 19:29
  • \$\begingroup\$ Do I understand correct that with SystemVerilog, all module exist in a flat hierarchy? There is also no concept of namespace? If so, then what happens if two modules have same name but is actually different module? \$\endgroup\$
    – quantum231
    Jan 25, 2022 at 20:37
  • \$\begingroup\$ @quantum231, SystemVerilog has multiple namespaces as defined in section 3.13 Name spaces. There is one global namespace for module names, but it's possible to tell the compiler to compile a module into a library, and then specify a ordered search list of libraries to scan for pre-compiled modules. None of that is specified in the LRM. \$\endgroup\$
    – dave_59
    Jan 25, 2022 at 22:24
  • \$\begingroup\$ Where can I find a more details description of what the concept of library and namespace in SystemVerilog is like? \$\endgroup\$
    – quantum231
    Feb 25, 2022 at 17:47

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