What is SystemVerilog equivalent for VHDL fixed_pkg and float_pkg?

Question

The VHDL fixed_pkg and float_pkg provide some very interesting functionality. The fixed_pkg is supported by some synthesis tools but the float_pkg is not supported at all. They basically provide a capability to declare a array of std_logic with positive and negative indices. This way one can create fixed point numbers and floating point numbers represented as array of std_logic.

I have not found anything like fixed_pkg and float_pkg for SystemVerilog so far. If something exists of this nature, where can I find it?

Answer 1

I think you can seemlessly use real, shortreal for float values whereas int for fixed data type values to perform arithmetic operations on variables.

Below is the note from systemverilog-3.1a:

"The real and shortreal types are represented as described by IEEE 754-1985, an IEEE standard for floating point numbers (See [K1] in Annex K)"

As added in snip below, you can see sign, mantissa and exponent part structure.