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Is it possible to get the following truth table to work using only 2 logic gates?

W and CHS are inputs, and S and R are outputs.

W CHS S R
0 0 0 0
0 1 0 0
1 0 1 0
1 1 0 1

Basically, I'm trying to control an SR flip-flop. With CHS, I want to select whether I set the flipflop or reset the flipflop, and with W, I want to write to the flipflop.

The problem is that I don't have enough space on my circuit board to fit more IC's. Is it possible to do this using just 2 logic gates?

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    \$\begingroup\$ Depends on what gates you’ve got available. Scope your question so it is not a guessing game. \$\endgroup\$
    – Kartman
    Jan 26 at 9:28
  • \$\begingroup\$ So if I understand you correctly, you want to create a D-Flip-Flop from an RS one? \$\endgroup\$
    – kruemi
    Jan 26 at 10:25

1 Answer 1

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It's possible to do it with three gates, two AND, one NOT as shown below. I list this option first because it uses two of the same gate (AND), and an inverter. Given the prevalence of single/dual logic gate ICs in tiny packages (e.g. TI Little Logic, Nexperia do equivalents), this may actually be the most compact circuit. A dual AND gate IC (8-pin) and an inverter (5-pin, or discrete transistor/resistor) would be sufficient.

Logic circuit with two AND and one NOT

Simulate

Alternatively, if you are desperate for a two gate solution, the following uses one AND and one XOR. Again using the little logic style ICs, this could be done with two 5-pin SC-70 packages (or smaller) making for a very compact circuit.

Logic circuit with AND and XOR Simulate

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  • \$\begingroup\$ I don't think it actually matters in this application, but both of your circuits have potential race hazards: when W and CHS are both high, and then W is brought low, S could briefly go high. If the output were driving an SR latch instead of a flip-flop, that could cause the latch to be set when it shouldn't be. In the first circuit, the race hazard can be eliminated by connecting the input of the inverter directly to CHS, instead of connecting it to the output of the other AND gate. \$\endgroup\$ Jan 26 at 12:17
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    \$\begingroup\$ @TannerSwett That's a fair point. I had actually intended for the inverter to be connected to CHS in the first circuit, made a mistake when drawing it out (still matches the truth table amusingly), have corrected that now. \$\endgroup\$ Jan 26 at 12:40
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    \$\begingroup\$ There is a single chip for AND with one inverted input. \$\endgroup\$
    – CL.
    Jan 26 at 19:32

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