# Maximum clock frequency for multi-cycle vs pipeline

Suppose you have latencies:

IF: 10 ns
ID: 11 ns
EX: 12 ns
MEM: 13 ns
WB: 14 ns


What is the maximum possible clock frequency for a pipeline with this design? I found information online that suggests the maximum possible clock frequency is 1/c, where c is the latency of the slowest stage. Thus, we have 1/14 GHz. Is this correct?

Also, how does this differ from a multi-cycle design? If we had latencies:

Register read: 1 ns Register write: 2 ns ALU: 3 ns Memory read/write: 4 ns

Wouldn't the maximum clock frequency also be 1/c, where c is the latency of the slowest stage? Thus, we would have 1/4 GHz.

In total, if my above calculations are correct, I'm curious as to why the multi-cycle and pipeline design internally depend on the same latency delay (the one that's slowest). Thanks for any help.