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Suppose you have latencies:

IF: 10 ns
ID: 11 ns
EX: 12 ns
MEM: 13 ns
WB: 14 ns

What is the maximum possible clock frequency for a pipeline with this design? I found information online that suggests the maximum possible clock frequency is 1/c, where c is the latency of the slowest stage. Thus, we have 1/14 GHz. Is this correct?

Also, how does this differ from a multi-cycle design? If we had latencies:

Register read: 1 ns Register write: 2 ns ALU: 3 ns Memory read/write: 4 ns

Wouldn't the maximum clock frequency also be 1/c, where c is the latency of the slowest stage? Thus, we would have 1/4 GHz.

In total, if my above calculations are correct, I'm curious as to why the multi-cycle and pipeline design internally depend on the same latency delay (the one that's slowest). Thanks for any help.

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Pipelined design: you are correct about 1/14GHz.

Multi-cycle: you can change the denominator. For your second example, you could have the ALU and memory stages take 2 cycles each, and run the whole thing at 2/4 GHz.

However, this affects throughput: if your ALU takes 2 cycles, you can't issue more than 1 ALU operation every 2 cycles. Whereas in your first example you can issue 1 instruction every cycle (assuming no stalls or branch mispredicts).

Multi-cycle designs are also a pain from a toolchain and verification perspective, as you have to tell all the tools "this path completes in 2 cycles, do not complain about paths that are longer than 1 cycle".

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