
simulate this circuit – Schematic created using CircuitLab
If the dV/dt is small, meaning dt >> dV and dV is ~ 1% then adding bulk very low ESR capacitors will filter only some of this instant change.
Otherwise, a compromise between digital filtering and expectations for decay time and standard-deviation comes from knowing why it changes.
This simple model is not enough as there are more than one RC equivalent circuit in every battery cell, the obvious parallel plates and the double-electric charge layers. But let's use it anyways.
\$V_{bat}= V_{C1} - I_{bat}*R_1\$
So there will be burst drops in decivolts due to I*R1 and gradual drops in mV due to C1 being discharged.
While batteries have ESR*C time constants in the order of seconds to minutes, low ESR e-caps have time constants on the order of 10 us ,so filtering above is only useful for preventing aliasing sampling errors in the step voltage changes due to burst loads.
The time constants are also extended greatly by increasing the resistance of the load ( reduce load current) relative to the source. This is almost the definition of Load Regulation Error. which is merely the ratio of source ESR to load R % or the measured Vdrop in % for rated current.
Recommendations:
1. Define the stability limits you want. i.e. tolerance spec
- Average your ADC results with fast enough resolution using statistics
- fast enough or slow down the step voltage from slew rate with a bulk cap R1(ESR)*C3 = T3 Let T3 > 5x sampling interval Ts to reduce aliasing error.
- Verify it meets spec (1.) (adjust if necessary)
- Decide if your battery ESR*C meets your TBD overall Load Regulation specs over time. Bigger is better and also some chemistries (Li Ion) are better than others like Al Ion.
6. Come up with better specs and test methods with DoE methods using Test Engineer's skills.
I've had these skills for many decades.