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I have to write a code to generate partial products for a 53*53 radix four booth multiplication. I declared a function as shown below; it is showing the error message MULTIPLE PACKED DIMENSION NOT ALLOWED IN VERILOG. Why?

function[27:0][107:0]boothans;(function declaration)
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    \$\begingroup\$ Your question seems incomplete, you mention the function as shown below but it's not there. You can edit your question to include it. \$\endgroup\$ – PeterJ Mar 12 '13 at 6:26
  • \$\begingroup\$ i wrote a very big function for it.But am getting error in the declaration line itself. \$\endgroup\$ – twinkle Mar 12 '13 at 6:41
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One of the "nice" ways of flattening an array is to choose an array size where the edge lengths are powers of 2. For example, you have sizes 108 and 28 bits. If you round those up to 128 and 32 bits, then you can concatenate the bit addresses together to get a "flat" array.

For example, say x is the 32 bit address and y is 128 bit address,

square[x][y] maps to flat[x + y << 32]

To work this out in verilog, you can loop through x and y in a nested fashion, and your new flat data address is {x,y} or {y,x} depending if you want your data row-wise or column-wise.

The other side is just a matter of reversing the process. It's trivial to pad the data with zeros where necessary, and it seems you are doing some padding in any case because your row lengths aren't the same.

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  • \$\begingroup\$ I don't recall if can you use bit concatenation in an array index? If you can, you'd just have flat[{y, x}] in your example. \$\endgroup\$ – The Photon Apr 11 '13 at 15:53
  • \$\begingroup\$ I don't know what the verilog syntax is, but in VHDL it's something I do on a regular basis. I just use two bit vectors, concatenate them together and cast as an int as the array index. if bit vectors can't be used, c-style works on integers (bit shift and mask). \$\endgroup\$ – stanri Apr 12 '13 at 5:09
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I think the error message says it all in your case. You just simply are not allowed to use an array as an input/output port of a module or function (at least not without SystemVerilog).

If you want to proceed, you'll have to flatten your 2d array into a 1d bus for passing into and out of the function.

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  • \$\begingroup\$ how do i flatten my 2d array into 1d bus? \$\endgroup\$ – twinkle Mar 12 '13 at 7:20
  • \$\begingroup\$ There's not a special function to do it or anything, you just have to declare a bus the width of the product of the dimensions, and assign the various slices of the array into the bus. For example if you were mapping a [10][10] array to 1D, you would declare a 100 bit bus, where slice [0] is [9:0], slice [1] is [19:10], etc. You can use a for loop to make it easier to implement if you desire. \$\endgroup\$ – Tim Mar 12 '13 at 7:28
  • \$\begingroup\$ length of each row in my case is different. ie, each partial product which i store will not have same number of bits. slicing will not be possible in that case rite? \$\endgroup\$ – twinkle Mar 12 '13 at 7:37
  • \$\begingroup\$ You've got to use slicing, and just leave the extra bits unused. Yes, this is pretty ugly, but there's no way round it. \$\endgroup\$ – pjc50 Mar 12 '13 at 12:04

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