I am designing a floating point unit in verilog. I have designed separate adder, shifter and multiplier modules in verilog. I want to call all these modules and make a single main module. I am not able to instantiate these modules inside always block, but I also need clock in my main module. How do I overcome this problem?

  • \$\begingroup\$ Should this not be on StackOverflow as it is a question about programming verilog? \$\endgroup\$ – pre_randomize Mar 12 '13 at 10:51

You can't instantiate modules in always block. Do it before and assign a clock to that module.

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  • \$\begingroup\$ i dint understand clearly. \$\endgroup\$ – twinkle Mar 12 '13 at 8:11
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    \$\begingroup\$ add Your source code snippet to pastebin. \$\endgroup\$ – Socrates Mar 12 '13 at 8:24
  • \$\begingroup\$ @Socrates please consider expanding your answer with some explanatory text suitable to the expertise level demonstrated in the question. \$\endgroup\$ – Anindo Ghosh Mar 12 '13 at 9:42
  • \$\begingroup\$ i have only the codes of my submodule. Did u mean that i should instantiate the modules first and then give clock in a seperate always block? will it serve the purpose of having a clock in my main module? \$\endgroup\$ – twinkle Mar 12 '13 at 11:10
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    \$\begingroup\$ You need to learn how to instantiate modules in top module first of all. Each module should have clock input, so just assign clock to that input. You don't have "to clock the module" somehow. The module itself is like a small design, that You have to provide clock to. I don't know how to give any better answer, when the OP doesn't know the basics of language he/she is designing. \$\endgroup\$ – Socrates Mar 12 '13 at 11:31

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