I'm having some difficulties in simulating this circuit in LTspice. I'm using op amps in the inverting configuration and buffers between each stage but it's simply not working. The simulation runs for several minutes and then the outputs of the stages come out all messy. I made the calculations and it is supposed to generate an sine wave with a frequency of about 90Hz. The Gain of each stage is supposed to be at least 2. Does anyone know to proper simulate this circuit? The capacitors and resistors are 100 nF and 10kOhm, respectively.
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\$\begingroup\$ Here is an LTspice example with a working ring oscillator. It might be useful to build around it. electronics.stackexchange.com/questions/594463/… \$\endgroup\$– patJan 31, 2022 at 3:38
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\$\begingroup\$ maybe try the alternate solver, that can help sometimes. Is the ground between the supply rails of the amplifiers? \$\endgroup\$– Jasen Слава УкраїніJan 31, 2022 at 3:42
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\$\begingroup\$ that circuit looks like a relaxation oscillator to me. \$\endgroup\$– Jasen Слава УкраїніJan 31, 2022 at 3:46
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\$\begingroup\$ I get \$f_{_0}\approx \frac1{2\pi\,R\,C}\$. With your values this is closer to 160 Hz. How do you get 90 Hz? \$\endgroup\$– jonkJan 31, 2022 at 3:47
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\$\begingroup\$ If you were to directly cascade the RC sections without buffering, then I'd find something more like \$f_{_0}\approx \frac1{4.2\,R\,C}\$ which would be closer to 76 Hz. But you've got buffering going on, so the successive passive loading effects aren't there. I need to see your theory and resulting quantitative calculations. \$\endgroup\$– jonkJan 31, 2022 at 4:29
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2 Answers
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Try the following
- Use ideal gain stages with gain of 2 each.
- Inject small current pulse to force startup. (note I saw jp314 earlier post after I simulated -- mostly same idea).
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\$\begingroup\$ Or create a small imbalance by adding e.g.
ic=1to one of the capacitors. It would be nice if OP set the gains to1for two of the VCVSs, and to{x}for any one of them. Then, adding a voltage source withAC 1in the feedback and using.step param x 6 10 1with.ac dec 101 1 1kwill clearly show the condition for oscillation. \$\endgroup\$ Jan 31, 2022 at 12:56 -
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If the 'K' elements are ideal components (no limitation on output voltage), then the circuit loop will have infinite gain and won't give reasonable results.
Put back-back diodes across each resistor.
Also, SPICE may not start an oscillation after it finds the DC bias point -- you may need to add a small perturbation to some node (e.g. a current source pulse that starts at 1 uA and switches to 0 at 1 us).
