What is the logic behind the behaviour of reg in Verilog?

Question

I know SystemVerilog and now I'm trying to learn pure Verilog. I find the way reg works to be rather odd. I thought wire is used for signals that are continuously driven like the output of combinational logic, and reg is used for signals that can retain their state, such as the output of flip flops or latches.

However I read that any signal assigned inside of an always block must be reg. Even if the behavior is modeling combinational logic, like in a case statement, which leads to the following weird situation:

Example a:

assign y = s ? a : b;

Example b:

always @* begin
    if (s)
         y = a;
    else
         y = b;
end

In example a y would be wire whereas in example b y must be reg. However they both describe the same thing. My only explanation for this is that within a combinational always it is possible to accidentally leave no specified output for some inputs, implying a latch which should be reg so they force it to always be reg.

Please help me understand the reasoning for how reg works in Verilog.

Answer 1

The keyword reg in Verilog is a misnomer and why it was renamed to logic in SystemVerilog. It is just a 4-state data type for a variable that could be interpreted as a hardware register or combinational signal.

The thing that makes it confusing for people starting in SystemVerilog and having to go back to Verilog is the single continuous driver rule. Wires are meant to handle multiple drivers with built-in resolution functions, but most signals only have a single driver. SystemVerilog made an exception so that variables could be continuously driven by a single driver. Then you can use variables for most everything only reverting to wires when you needed multiple drivers, like a bidirectional bus.

See this webpage for more explicit details.